imxrt_ral/blocks/imxrt1011/
spdif.rs
1#[doc = "SPDIF"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "SPDIF Configuration Register"]
5 pub SCR: crate::RWRegister<u32>,
6 #[doc = "CDText Control Register"]
7 pub SRCD: crate::RWRegister<u32>,
8 #[doc = "PhaseConfig Register"]
9 pub SRPC: crate::RWRegister<u32>,
10 #[doc = "InterruptEn Register"]
11 pub SIE: crate::RWRegister<u32>,
12 #[doc = "InterruptClear Register"]
13 pub SIC: crate::RWRegister<u32>,
14 #[doc = "SPDIFRxLeft Register"]
15 pub SRL: crate::RORegister<u32>,
16 #[doc = "SPDIFRxRight Register"]
17 pub SRR: crate::RORegister<u32>,
18 #[doc = "SPDIFRxCChannel_h Register"]
19 pub SRCSH: crate::RORegister<u32>,
20 #[doc = "SPDIFRxCChannel_l Register"]
21 pub SRCSL: crate::RORegister<u32>,
22 #[doc = "UchannelRx Register"]
23 pub SRU: crate::RORegister<u32>,
24 #[doc = "QchannelRx Register"]
25 pub SRQ: crate::RORegister<u32>,
26 #[doc = "SPDIFTxLeft Register"]
27 pub STL: crate::RWRegister<u32>,
28 #[doc = "SPDIFTxRight Register"]
29 pub STR: crate::RWRegister<u32>,
30 #[doc = "SPDIFTxCChannelCons_h Register"]
31 pub STCSCH: crate::RWRegister<u32>,
32 #[doc = "SPDIFTxCChannelCons_l Register"]
33 pub STCSCL: crate::RWRegister<u32>,
34 _reserved0: [u8; 0x08],
35 #[doc = "FreqMeas Register"]
36 pub SRFM: crate::RORegister<u32>,
37 _reserved1: [u8; 0x08],
38 #[doc = "SPDIFTxClk Register"]
39 pub STC: crate::RWRegister<u32>,
40}
41#[doc = "SPDIF Configuration Register"]
42pub mod SCR {
43 #[doc = "no description available"]
44 pub mod USRC_SEL {
45 pub const offset: u32 = 0;
46 pub const mask: u32 = 0x03 << offset;
47 pub mod R {}
48 pub mod W {}
49 pub mod RW {
50 #[doc = "No embedded U channel"]
51 pub const USRC_SEL_0: u32 = 0;
52 #[doc = "U channel from SPDIF receive block (CD mode)"]
53 pub const USRC_SEL_1: u32 = 0x01;
54 #[doc = "U channel from on chip transmitter"]
55 pub const USRC_SEL_3: u32 = 0x03;
56 }
57 }
58 #[doc = "no description available"]
59 pub mod TXSEL {
60 pub const offset: u32 = 2;
61 pub const mask: u32 = 0x07 << offset;
62 pub mod R {}
63 pub mod W {}
64 pub mod RW {
65 #[doc = "Off and output 0"]
66 pub const TXSEL_0: u32 = 0;
67 #[doc = "Feed-through SPDIFIN"]
68 pub const TXSEL_1: u32 = 0x01;
69 #[doc = "Tx Normal operation"]
70 pub const TXSEL_5: u32 = 0x05;
71 }
72 }
73 #[doc = "no description available"]
74 pub mod VALCTRL {
75 pub const offset: u32 = 5;
76 pub const mask: u32 = 0x01 << offset;
77 pub mod R {}
78 pub mod W {}
79 pub mod RW {
80 #[doc = "Outgoing Validity always set"]
81 pub const VALCTRL_0: u32 = 0;
82 #[doc = "Outgoing Validity always clear"]
83 pub const VALCTRL_1: u32 = 0x01;
84 }
85 }
86 #[doc = "DMA Transmit Request Enable (Tx FIFO empty)"]
87 pub mod DMA_TX_EN {
88 pub const offset: u32 = 8;
89 pub const mask: u32 = 0x01 << offset;
90 pub mod R {}
91 pub mod W {}
92 pub mod RW {}
93 }
94 #[doc = "DMA Receive Request Enable (RX FIFO full)"]
95 pub mod DMA_RX_EN {
96 pub const offset: u32 = 9;
97 pub const mask: u32 = 0x01 << offset;
98 pub mod R {}
99 pub mod W {}
100 pub mod RW {}
101 }
102 #[doc = "no description available"]
103 pub mod TXFIFO_CTRL {
104 pub const offset: u32 = 10;
105 pub const mask: u32 = 0x03 << offset;
106 pub mod R {}
107 pub mod W {}
108 pub mod RW {
109 #[doc = "Send out digital zero on SPDIF Tx"]
110 pub const TXFIFO_CTRL_0: u32 = 0;
111 #[doc = "Tx Normal operation"]
112 pub const TXFIFO_CTRL_1: u32 = 0x01;
113 #[doc = "Reset to 1 sample remaining"]
114 pub const TXFIFO_CTRL_2: u32 = 0x02;
115 }
116 }
117 #[doc = "When write 1 to this bit, it will cause SPDIF software reset"]
118 pub mod SOFT_RESET {
119 pub const offset: u32 = 12;
120 pub const mask: u32 = 0x01 << offset;
121 pub mod R {}
122 pub mod W {}
123 pub mod RW {}
124 }
125 #[doc = "When write 1 to this bit, it will cause SPDIF enter low-power mode"]
126 pub mod LOW_POWER {
127 pub const offset: u32 = 13;
128 pub const mask: u32 = 0x01 << offset;
129 pub mod R {}
130 pub mod W {}
131 pub mod RW {}
132 }
133 #[doc = "no description available"]
134 pub mod TXFIFOEMPTY_SEL {
135 pub const offset: u32 = 15;
136 pub const mask: u32 = 0x03 << offset;
137 pub mod R {}
138 pub mod W {}
139 pub mod RW {
140 #[doc = "Empty interrupt if 0 sample in Tx left and right FIFOs"]
141 pub const TXFIFOEMPTY_SEL_0: u32 = 0;
142 #[doc = "Empty interrupt if at most 4 sample in Tx left and right FIFOs"]
143 pub const TXFIFOEMPTY_SEL_1: u32 = 0x01;
144 #[doc = "Empty interrupt if at most 8 sample in Tx left and right FIFOs"]
145 pub const TXFIFOEMPTY_SEL_2: u32 = 0x02;
146 #[doc = "Empty interrupt if at most 12 sample in Tx left and right FIFOs"]
147 pub const TXFIFOEMPTY_SEL_3: u32 = 0x03;
148 }
149 }
150 #[doc = "no description available"]
151 pub mod TXAUTOSYNC {
152 pub const offset: u32 = 17;
153 pub const mask: u32 = 0x01 << offset;
154 pub mod R {}
155 pub mod W {}
156 pub mod RW {
157 #[doc = "Tx FIFO auto sync off"]
158 pub const TXAUTOSYNC_0: u32 = 0;
159 #[doc = "Tx FIFO auto sync on"]
160 pub const TXAUTOSYNC_1: u32 = 0x01;
161 }
162 }
163 #[doc = "no description available"]
164 pub mod RXAUTOSYNC {
165 pub const offset: u32 = 18;
166 pub const mask: u32 = 0x01 << offset;
167 pub mod R {}
168 pub mod W {}
169 pub mod RW {
170 #[doc = "Rx FIFO auto sync off"]
171 pub const RXAUTOSYNC_0: u32 = 0;
172 #[doc = "RxFIFO auto sync on"]
173 pub const RXAUTOSYNC_1: u32 = 0x01;
174 }
175 }
176 #[doc = "no description available"]
177 pub mod RXFIFOFULL_SEL {
178 pub const offset: u32 = 19;
179 pub const mask: u32 = 0x03 << offset;
180 pub mod R {}
181 pub mod W {}
182 pub mod RW {
183 #[doc = "Full interrupt if at least 1 sample in Rx left and right FIFOs"]
184 pub const RXFIFOFULL_SEL_0: u32 = 0;
185 #[doc = "Full interrupt if at least 4 sample in Rx left and right FIFOs"]
186 pub const RXFIFOFULL_SEL_1: u32 = 0x01;
187 #[doc = "Full interrupt if at least 8 sample in Rx left and right FIFOs"]
188 pub const RXFIFOFULL_SEL_2: u32 = 0x02;
189 #[doc = "Full interrupt if at least 16 sample in Rx left and right FIFO"]
190 pub const RXFIFOFULL_SEL_3: u32 = 0x03;
191 }
192 }
193 #[doc = "no description available"]
194 pub mod RXFIFO_RST {
195 pub const offset: u32 = 21;
196 pub const mask: u32 = 0x01 << offset;
197 pub mod R {}
198 pub mod W {}
199 pub mod RW {
200 #[doc = "Normal operation"]
201 pub const RXFIFO_RST_0: u32 = 0;
202 #[doc = "Reset register to 1 sample remaining"]
203 pub const RXFIFO_RST_1: u32 = 0x01;
204 }
205 }
206 #[doc = "no description available"]
207 pub mod RXFIFO_OFF_ON {
208 pub const offset: u32 = 22;
209 pub const mask: u32 = 0x01 << offset;
210 pub mod R {}
211 pub mod W {}
212 pub mod RW {
213 #[doc = "SPDIF Rx FIFO is on"]
214 pub const RXFIFO_OFF_ON_0: u32 = 0;
215 #[doc = "SPDIF Rx FIFO is off. Does not accept data from interface"]
216 pub const RXFIFO_OFF_ON_1: u32 = 0x01;
217 }
218 }
219 #[doc = "no description available"]
220 pub mod RXFIFO_CTRL {
221 pub const offset: u32 = 23;
222 pub const mask: u32 = 0x01 << offset;
223 pub mod R {}
224 pub mod W {}
225 pub mod RW {
226 #[doc = "Normal operation"]
227 pub const RXFIFO_CTRL_0: u32 = 0;
228 #[doc = "Always read zero from Rx data register"]
229 pub const RXFIFO_CTRL_1: u32 = 0x01;
230 }
231 }
232}
233#[doc = "CDText Control Register"]
234pub mod SRCD {
235 #[doc = "no description available"]
236 pub mod USYNCMODE {
237 pub const offset: u32 = 1;
238 pub const mask: u32 = 0x01 << offset;
239 pub mod R {}
240 pub mod W {}
241 pub mod RW {
242 #[doc = "Non-CD data"]
243 pub const USYNCMODE_0: u32 = 0;
244 #[doc = "CD user channel subcode"]
245 pub const USYNCMODE_1: u32 = 0x01;
246 }
247 }
248}
249#[doc = "PhaseConfig Register"]
250pub mod SRPC {
251 #[doc = "Gain selection:"]
252 pub mod GAINSEL {
253 pub const offset: u32 = 3;
254 pub const mask: u32 = 0x07 << offset;
255 pub mod R {}
256 pub mod W {}
257 pub mod RW {
258 #[doc = "24*(2**10)"]
259 pub const GAINSEL_0: u32 = 0;
260 #[doc = "16*(2**10)"]
261 pub const GAINSEL_1: u32 = 0x01;
262 #[doc = "12*(2**10)"]
263 pub const GAINSEL_2: u32 = 0x02;
264 #[doc = "8*(2**10)"]
265 pub const GAINSEL_3: u32 = 0x03;
266 #[doc = "6*(2**10)"]
267 pub const GAINSEL_4: u32 = 0x04;
268 #[doc = "4*(2**10)"]
269 pub const GAINSEL_5: u32 = 0x05;
270 #[doc = "3*(2**10)"]
271 pub const GAINSEL_6: u32 = 0x06;
272 }
273 }
274 #[doc = "LOCK bit to show that the internal DPLL is locked, read only"]
275 pub mod LOCK {
276 pub const offset: u32 = 6;
277 pub const mask: u32 = 0x01 << offset;
278 pub mod R {}
279 pub mod W {}
280 pub mod RW {}
281 }
282 #[doc = "Clock source selection, all other settings not shown are reserved:"]
283 pub mod CLKSRC_SEL {
284 pub const offset: u32 = 7;
285 pub const mask: u32 = 0x0f << offset;
286 pub mod R {}
287 pub mod W {}
288 pub mod RW {
289 #[doc = "if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)"]
290 pub const CLKSRC_SEL_0: u32 = 0;
291 #[doc = "if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)"]
292 pub const CLKSRC_SEL_1: u32 = 0x01;
293 #[doc = "if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK"]
294 pub const CLKSRC_SEL_3: u32 = 0x03;
295 #[doc = "REF_CLK_32K (XTALOSC)"]
296 pub const CLKSRC_SEL_5: u32 = 0x05;
297 #[doc = "tx_clk (SPDIF0_CLK_ROOT)"]
298 pub const CLKSRC_SEL_6: u32 = 0x06;
299 #[doc = "SPDIF_EXT_CLK"]
300 pub const CLKSRC_SEL_8: u32 = 0x08;
301 }
302 }
303}
304#[doc = "InterruptEn Register"]
305pub mod SIE {
306 #[doc = "SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO."]
307 pub mod RXFIFOFUL {
308 pub const offset: u32 = 0;
309 pub const mask: u32 = 0x01 << offset;
310 pub mod R {}
311 pub mod W {}
312 pub mod RW {}
313 }
314 #[doc = "SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO."]
315 pub mod TXEM {
316 pub const offset: u32 = 1;
317 pub const mask: u32 = 0x01 << offset;
318 pub mod R {}
319 pub mod W {}
320 pub mod RW {}
321 }
322 #[doc = "SPDIF receiver loss of lock"]
323 pub mod LOCKLOSS {
324 pub const offset: u32 = 2;
325 pub const mask: u32 = 0x01 << offset;
326 pub mod R {}
327 pub mod W {}
328 pub mod RW {}
329 }
330 #[doc = "Rx FIFO resync"]
331 pub mod RXFIFORESYN {
332 pub const offset: u32 = 3;
333 pub const mask: u32 = 0x01 << offset;
334 pub mod R {}
335 pub mod W {}
336 pub mod RW {}
337 }
338 #[doc = "Rx FIFO underrun/overrun"]
339 pub mod RXFIFOUNOV {
340 pub const offset: u32 = 4;
341 pub const mask: u32 = 0x01 << offset;
342 pub mod R {}
343 pub mod W {}
344 pub mod RW {}
345 }
346 #[doc = "U/Q Channel framing error"]
347 pub mod UQERR {
348 pub const offset: u32 = 5;
349 pub const mask: u32 = 0x01 << offset;
350 pub mod R {}
351 pub mod W {}
352 pub mod RW {}
353 }
354 #[doc = "U/Q Channel sync found"]
355 pub mod UQSYNC {
356 pub const offset: u32 = 6;
357 pub const mask: u32 = 0x01 << offset;
358 pub mod R {}
359 pub mod W {}
360 pub mod RW {}
361 }
362 #[doc = "Q Channel receive register overrun"]
363 pub mod QRXOV {
364 pub const offset: u32 = 7;
365 pub const mask: u32 = 0x01 << offset;
366 pub mod R {}
367 pub mod W {}
368 pub mod RW {}
369 }
370 #[doc = "Q Channel receive register full, can't be cleared with reg"]
371 pub mod QRXFUL {
372 pub const offset: u32 = 8;
373 pub const mask: u32 = 0x01 << offset;
374 pub mod R {}
375 pub mod W {}
376 pub mod RW {}
377 }
378 #[doc = "U Channel receive register overrun"]
379 pub mod URXOV {
380 pub const offset: u32 = 9;
381 pub const mask: u32 = 0x01 << offset;
382 pub mod R {}
383 pub mod W {}
384 pub mod RW {}
385 }
386 #[doc = "U Channel receive register full, can't be cleared with reg"]
387 pub mod URXFUL {
388 pub const offset: u32 = 10;
389 pub const mask: u32 = 0x01 << offset;
390 pub mod R {}
391 pub mod W {}
392 pub mod RW {}
393 }
394 #[doc = "SPDIF receiver found parity bit error"]
395 pub mod BITERR {
396 pub const offset: u32 = 14;
397 pub const mask: u32 = 0x01 << offset;
398 pub mod R {}
399 pub mod W {}
400 pub mod RW {}
401 }
402 #[doc = "SPDIF receiver found illegal symbol"]
403 pub mod SYMERR {
404 pub const offset: u32 = 15;
405 pub const mask: u32 = 0x01 << offset;
406 pub mod R {}
407 pub mod W {}
408 pub mod RW {}
409 }
410 #[doc = "SPDIF validity flag no good"]
411 pub mod VALNOGOOD {
412 pub const offset: u32 = 16;
413 pub const mask: u32 = 0x01 << offset;
414 pub mod R {}
415 pub mod W {}
416 pub mod RW {}
417 }
418 #[doc = "SPDIF receive change in value of control channel"]
419 pub mod CNEW {
420 pub const offset: u32 = 17;
421 pub const mask: u32 = 0x01 << offset;
422 pub mod R {}
423 pub mod W {}
424 pub mod RW {}
425 }
426 #[doc = "SPDIF Tx FIFO resync"]
427 pub mod TXRESYN {
428 pub const offset: u32 = 18;
429 pub const mask: u32 = 0x01 << offset;
430 pub mod R {}
431 pub mod W {}
432 pub mod RW {}
433 }
434 #[doc = "SPDIF Tx FIFO under/overrun"]
435 pub mod TXUNOV {
436 pub const offset: u32 = 19;
437 pub const mask: u32 = 0x01 << offset;
438 pub mod R {}
439 pub mod W {}
440 pub mod RW {}
441 }
442 #[doc = "SPDIF receiver's DPLL is locked"]
443 pub mod LOCK {
444 pub const offset: u32 = 20;
445 pub const mask: u32 = 0x01 << offset;
446 pub mod R {}
447 pub mod W {}
448 pub mod RW {}
449 }
450}
451#[doc = "InterruptClear Register"]
452pub mod SIC {
453 #[doc = "SPDIF receiver loss of lock"]
454 pub mod LOCKLOSS {
455 pub const offset: u32 = 2;
456 pub const mask: u32 = 0x01 << offset;
457 pub mod R {}
458 pub mod W {}
459 pub mod RW {}
460 }
461 #[doc = "Rx FIFO resync"]
462 pub mod RXFIFORESYN {
463 pub const offset: u32 = 3;
464 pub const mask: u32 = 0x01 << offset;
465 pub mod R {}
466 pub mod W {}
467 pub mod RW {}
468 }
469 #[doc = "Rx FIFO underrun/overrun"]
470 pub mod RXFIFOUNOV {
471 pub const offset: u32 = 4;
472 pub const mask: u32 = 0x01 << offset;
473 pub mod R {}
474 pub mod W {}
475 pub mod RW {}
476 }
477 #[doc = "U/Q Channel framing error"]
478 pub mod UQERR {
479 pub const offset: u32 = 5;
480 pub const mask: u32 = 0x01 << offset;
481 pub mod R {}
482 pub mod W {}
483 pub mod RW {}
484 }
485 #[doc = "U/Q Channel sync found"]
486 pub mod UQSYNC {
487 pub const offset: u32 = 6;
488 pub const mask: u32 = 0x01 << offset;
489 pub mod R {}
490 pub mod W {}
491 pub mod RW {}
492 }
493 #[doc = "Q Channel receive register overrun"]
494 pub mod QRXOV {
495 pub const offset: u32 = 7;
496 pub const mask: u32 = 0x01 << offset;
497 pub mod R {}
498 pub mod W {}
499 pub mod RW {}
500 }
501 #[doc = "U Channel receive register overrun"]
502 pub mod URXOV {
503 pub const offset: u32 = 9;
504 pub const mask: u32 = 0x01 << offset;
505 pub mod R {}
506 pub mod W {}
507 pub mod RW {}
508 }
509 #[doc = "SPDIF receiver found parity bit error"]
510 pub mod BITERR {
511 pub const offset: u32 = 14;
512 pub const mask: u32 = 0x01 << offset;
513 pub mod R {}
514 pub mod W {}
515 pub mod RW {}
516 }
517 #[doc = "SPDIF receiver found illegal symbol"]
518 pub mod SYMERR {
519 pub const offset: u32 = 15;
520 pub const mask: u32 = 0x01 << offset;
521 pub mod R {}
522 pub mod W {}
523 pub mod RW {}
524 }
525 #[doc = "SPDIF validity flag no good"]
526 pub mod VALNOGOOD {
527 pub const offset: u32 = 16;
528 pub const mask: u32 = 0x01 << offset;
529 pub mod R {}
530 pub mod W {}
531 pub mod RW {}
532 }
533 #[doc = "SPDIF receive change in value of control channel"]
534 pub mod CNEW {
535 pub const offset: u32 = 17;
536 pub const mask: u32 = 0x01 << offset;
537 pub mod R {}
538 pub mod W {}
539 pub mod RW {}
540 }
541 #[doc = "SPDIF Tx FIFO resync"]
542 pub mod TXRESYN {
543 pub const offset: u32 = 18;
544 pub const mask: u32 = 0x01 << offset;
545 pub mod R {}
546 pub mod W {}
547 pub mod RW {}
548 }
549 #[doc = "SPDIF Tx FIFO under/overrun"]
550 pub mod TXUNOV {
551 pub const offset: u32 = 19;
552 pub const mask: u32 = 0x01 << offset;
553 pub mod R {}
554 pub mod W {}
555 pub mod RW {}
556 }
557 #[doc = "SPDIF receiver's DPLL is locked"]
558 pub mod LOCK {
559 pub const offset: u32 = 20;
560 pub const mask: u32 = 0x01 << offset;
561 pub mod R {}
562 pub mod W {}
563 pub mod RW {}
564 }
565}
566#[doc = "SPDIFRxLeft Register"]
567pub mod SRL {
568 #[doc = "Processor receive SPDIF data left"]
569 pub mod RXDATALEFT {
570 pub const offset: u32 = 0;
571 pub const mask: u32 = 0x00ff_ffff << offset;
572 pub mod R {}
573 pub mod W {}
574 pub mod RW {}
575 }
576}
577#[doc = "SPDIFRxRight Register"]
578pub mod SRR {
579 #[doc = "Processor receive SPDIF data right"]
580 pub mod RXDATARIGHT {
581 pub const offset: u32 = 0;
582 pub const mask: u32 = 0x00ff_ffff << offset;
583 pub mod R {}
584 pub mod W {}
585 pub mod RW {}
586 }
587}
588#[doc = "SPDIFRxCChannel_h Register"]
589pub mod SRCSH {
590 #[doc = "SPDIF receive C channel register, contains first 24 bits of C channel without interpretation"]
591 pub mod RXCCHANNEL_H {
592 pub const offset: u32 = 0;
593 pub const mask: u32 = 0x00ff_ffff << offset;
594 pub mod R {}
595 pub mod W {}
596 pub mod RW {}
597 }
598}
599#[doc = "SPDIFRxCChannel_l Register"]
600pub mod SRCSL {
601 #[doc = "SPDIF receive C channel register, contains next 24 bits of C channel without interpretation"]
602 pub mod RXCCHANNEL_L {
603 pub const offset: u32 = 0;
604 pub const mask: u32 = 0x00ff_ffff << offset;
605 pub mod R {}
606 pub mod W {}
607 pub mod RW {}
608 }
609}
610#[doc = "UchannelRx Register"]
611pub mod SRU {
612 #[doc = "SPDIF receive U channel register, contains next 3 U channel bytes"]
613 pub mod RXUCHANNEL {
614 pub const offset: u32 = 0;
615 pub const mask: u32 = 0x00ff_ffff << offset;
616 pub mod R {}
617 pub mod W {}
618 pub mod RW {}
619 }
620}
621#[doc = "QchannelRx Register"]
622pub mod SRQ {
623 #[doc = "SPDIF receive Q channel register, contains next 3 Q channel bytes"]
624 pub mod RXQCHANNEL {
625 pub const offset: u32 = 0;
626 pub const mask: u32 = 0x00ff_ffff << offset;
627 pub mod R {}
628 pub mod W {}
629 pub mod RW {}
630 }
631}
632#[doc = "SPDIFTxLeft Register"]
633pub mod STL {
634 #[doc = "SPDIF transmit left channel data. It is write-only, and always returns zeros when read"]
635 pub mod TXDATALEFT {
636 pub const offset: u32 = 0;
637 pub const mask: u32 = 0x00ff_ffff << offset;
638 pub mod R {}
639 pub mod W {}
640 pub mod RW {}
641 }
642}
643#[doc = "SPDIFTxRight Register"]
644pub mod STR {
645 #[doc = "SPDIF transmit right channel data. It is write-only, and always returns zeros when read"]
646 pub mod TXDATARIGHT {
647 pub const offset: u32 = 0;
648 pub const mask: u32 = 0x00ff_ffff << offset;
649 pub mod R {}
650 pub mod W {}
651 pub mod RW {}
652 }
653}
654#[doc = "SPDIFTxCChannelCons_h Register"]
655pub mod STCSCH {
656 #[doc = "SPDIF transmit Cons"]
657 pub mod TXCCHANNELCONS_H {
658 pub const offset: u32 = 0;
659 pub const mask: u32 = 0x00ff_ffff << offset;
660 pub mod R {}
661 pub mod W {}
662 pub mod RW {}
663 }
664}
665#[doc = "SPDIFTxCChannelCons_l Register"]
666pub mod STCSCL {
667 #[doc = "SPDIF transmit Cons"]
668 pub mod TXCCHANNELCONS_L {
669 pub const offset: u32 = 0;
670 pub const mask: u32 = 0x00ff_ffff << offset;
671 pub mod R {}
672 pub mod W {}
673 pub mod RW {}
674 }
675}
676#[doc = "FreqMeas Register"]
677pub mod SRFM {
678 #[doc = "Frequency measurement data"]
679 pub mod FREQMEAS {
680 pub const offset: u32 = 0;
681 pub const mask: u32 = 0x00ff_ffff << offset;
682 pub mod R {}
683 pub mod W {}
684 pub mod RW {}
685 }
686}
687#[doc = "SPDIFTxClk Register"]
688pub mod STC {
689 #[doc = "Divider factor (1-128)"]
690 pub mod TXCLK_DF {
691 pub const offset: u32 = 0;
692 pub const mask: u32 = 0x7f << offset;
693 pub mod R {}
694 pub mod W {}
695 pub mod RW {
696 #[doc = "divider factor is 1"]
697 pub const TXCLK_DF_0: u32 = 0;
698 #[doc = "divider factor is 2"]
699 pub const TXCLK_DF_1: u32 = 0x01;
700 #[doc = "divider factor is 128"]
701 pub const TXCLK_DF_127: u32 = 0x7f;
702 }
703 }
704 #[doc = "Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1."]
705 pub mod TX_ALL_CLK_EN {
706 pub const offset: u32 = 7;
707 pub const mask: u32 = 0x01 << offset;
708 pub mod R {}
709 pub mod W {}
710 pub mod RW {
711 #[doc = "disable transfer clock."]
712 pub const TX_ALL_CLK_EN_0: u32 = 0;
713 #[doc = "enable transfer clock."]
714 pub const TX_ALL_CLK_EN_1: u32 = 0x01;
715 }
716 }
717 #[doc = "no description available"]
718 pub mod TXCLK_SOURCE {
719 pub const offset: u32 = 8;
720 pub const mask: u32 = 0x07 << offset;
721 pub mod R {}
722 pub mod W {}
723 pub mod RW {
724 #[doc = "XTALOSC input (XTALOSC clock)"]
725 pub const TXCLK_SOURCE_0: u32 = 0;
726 #[doc = "tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)"]
727 pub const TXCLK_SOURCE_1: u32 = 0x01;
728 #[doc = "tx_clk1 (from SAI1)"]
729 pub const TXCLK_SOURCE_2: u32 = 0x02;
730 #[doc = "tx_clk2 SPDIF_EXT_CLK, from pads"]
731 pub const TXCLK_SOURCE_3: u32 = 0x03;
732 #[doc = "tx_clk3 (from SAI2)"]
733 pub const TXCLK_SOURCE_4: u32 = 0x04;
734 #[doc = "ipg_clk input (frequency divided)"]
735 pub const TXCLK_SOURCE_5: u32 = 0x05;
736 #[doc = "tx_clk4 (from SAI3)"]
737 pub const TXCLK_SOURCE_6: u32 = 0x06;
738 }
739 }
740 #[doc = "system clock divider factor, 2~512."]
741 pub mod SYSCLK_DF {
742 pub const offset: u32 = 11;
743 pub const mask: u32 = 0x01ff << offset;
744 pub mod R {}
745 pub mod W {}
746 pub mod RW {
747 #[doc = "no clock signal"]
748 pub const SYSCLK_DF_0: u32 = 0;
749 #[doc = "divider factor is 2"]
750 pub const SYSCLK_DF_1: u32 = 0x01;
751 #[doc = "divider factor is 512"]
752 pub const SYSCLK_DF_511: u32 = 0x01ff;
753 }
754 }
755}