imxrt_ral/blocks/imxrt1011/
flexram.rs

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1#[doc = "FLEXRAM"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "TCM CRTL Register"]
5    pub TCM_CTRL: crate::RWRegister<u32>,
6    #[doc = "OCRAM Magic Address Register"]
7    pub OCRAM_MAGIC_ADDR: crate::RWRegister<u32>,
8    #[doc = "DTCM Magic Address Register"]
9    pub DTCM_MAGIC_ADDR: crate::RWRegister<u32>,
10    #[doc = "ITCM Magic Address Register"]
11    pub ITCM_MAGIC_ADDR: crate::RWRegister<u32>,
12    #[doc = "Interrupt Status Register"]
13    pub INT_STATUS: crate::RWRegister<u32>,
14    #[doc = "Interrupt Status Enable Register"]
15    pub INT_STAT_EN: crate::RWRegister<u32>,
16    #[doc = "Interrupt Enable Register"]
17    pub INT_SIG_EN: crate::RWRegister<u32>,
18}
19#[doc = "TCM CRTL Register"]
20pub mod TCM_CTRL {
21    #[doc = "TCM Write Wait Mode Enable"]
22    pub mod TCM_WWAIT_EN {
23        pub const offset: u32 = 0;
24        pub const mask: u32 = 0x01 << offset;
25        pub mod R {}
26        pub mod W {}
27        pub mod RW {
28            #[doc = "TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle."]
29            pub const TCM_WWAIT_EN_0: u32 = 0;
30            #[doc = "TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles."]
31            pub const TCM_WWAIT_EN_1: u32 = 0x01;
32        }
33    }
34    #[doc = "TCM Read Wait Mode Enable"]
35    pub mod TCM_RWAIT_EN {
36        pub const offset: u32 = 1;
37        pub const mask: u32 = 0x01 << offset;
38        pub mod R {}
39        pub mod W {}
40        pub mod RW {
41            #[doc = "TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle."]
42            pub const TCM_RWAIT_EN_0: u32 = 0;
43            #[doc = "TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles."]
44            pub const TCM_RWAIT_EN_1: u32 = 0x01;
45        }
46    }
47    #[doc = "Force RAM Clock Always On"]
48    pub mod FORCE_CLK_ON {
49        pub const offset: u32 = 2;
50        pub const mask: u32 = 0x01 << offset;
51        pub mod R {}
52        pub mod W {}
53        pub mod RW {}
54    }
55}
56#[doc = "OCRAM Magic Address Register"]
57pub mod OCRAM_MAGIC_ADDR {
58    #[doc = "OCRAM Write Read Select"]
59    pub mod OCRAM_WR_RD_SEL {
60        pub const offset: u32 = 0;
61        pub const mask: u32 = 0x01 << offset;
62        pub mod R {}
63        pub mod W {}
64        pub mod RW {
65            #[doc = "When OCRAM read access hits magic address, it will generate interrupt."]
66            pub const OCRAM_WR_RD_SEL_0: u32 = 0;
67            #[doc = "When OCRAM write access hits magic address, it will generate interrupt."]
68            pub const OCRAM_WR_RD_SEL_1: u32 = 0x01;
69        }
70    }
71    #[doc = "OCRAM Magic Address"]
72    pub mod OCRAM_MAGIC_ADDR {
73        pub const offset: u32 = 1;
74        pub const mask: u32 = 0x3fff << offset;
75        pub mod R {}
76        pub mod W {}
77        pub mod RW {}
78    }
79}
80#[doc = "DTCM Magic Address Register"]
81pub mod DTCM_MAGIC_ADDR {
82    #[doc = "DTCM Write Read Select"]
83    pub mod DTCM_WR_RD_SEL {
84        pub const offset: u32 = 0;
85        pub const mask: u32 = 0x01 << offset;
86        pub mod R {}
87        pub mod W {}
88        pub mod RW {
89            #[doc = "When DTCM read access hits magic address, it will generate interrupt."]
90            pub const DTCM_WR_RD_SEL_0: u32 = 0;
91            #[doc = "When DTCM write access hits magic address, it will generate interrupt."]
92            pub const DTCM_WR_RD_SEL_1: u32 = 0x01;
93        }
94    }
95    #[doc = "DTCM Magic Address"]
96    pub mod DTCM_MAGIC_ADDR {
97        pub const offset: u32 = 1;
98        pub const mask: u32 = 0x3fff << offset;
99        pub mod R {}
100        pub mod W {}
101        pub mod RW {}
102    }
103}
104#[doc = "ITCM Magic Address Register"]
105pub mod ITCM_MAGIC_ADDR {
106    #[doc = "ITCM Write Read Select"]
107    pub mod ITCM_WR_RD_SEL {
108        pub const offset: u32 = 0;
109        pub const mask: u32 = 0x01 << offset;
110        pub mod R {}
111        pub mod W {}
112        pub mod RW {
113            #[doc = "When ITCM read access hits magic address, it will generate interrupt."]
114            pub const ITCM_WR_RD_SEL_0: u32 = 0;
115            #[doc = "When ITCM write access hits magic address, it will generate interrupt."]
116            pub const ITCM_WR_RD_SEL_1: u32 = 0x01;
117        }
118    }
119    #[doc = "ITCM Magic Address"]
120    pub mod ITCM_MAGIC_ADDR {
121        pub const offset: u32 = 1;
122        pub const mask: u32 = 0x3fff << offset;
123        pub mod R {}
124        pub mod W {}
125        pub mod RW {}
126    }
127}
128#[doc = "Interrupt Status Register"]
129pub mod INT_STATUS {
130    #[doc = "ITCM Magic Address Match Status"]
131    pub mod ITCM_MAM_STATUS {
132        pub const offset: u32 = 0;
133        pub const mask: u32 = 0x01 << offset;
134        pub mod R {}
135        pub mod W {}
136        pub mod RW {
137            #[doc = "ITCM did not access magic address."]
138            pub const ITCM_MAM_STATUS_0: u32 = 0;
139            #[doc = "ITCM accessed magic address."]
140            pub const ITCM_MAM_STATUS_1: u32 = 0x01;
141        }
142    }
143    #[doc = "DTCM Magic Address Match Status"]
144    pub mod DTCM_MAM_STATUS {
145        pub const offset: u32 = 1;
146        pub const mask: u32 = 0x01 << offset;
147        pub mod R {}
148        pub mod W {}
149        pub mod RW {
150            #[doc = "DTCM did not access magic address."]
151            pub const DTCM_MAM_STATUS_0: u32 = 0;
152            #[doc = "DTCM accessed magic address."]
153            pub const DTCM_MAM_STATUS_1: u32 = 0x01;
154        }
155    }
156    #[doc = "OCRAM Magic Address Match Status"]
157    pub mod OCRAM_MAM_STATUS {
158        pub const offset: u32 = 2;
159        pub const mask: u32 = 0x01 << offset;
160        pub mod R {}
161        pub mod W {}
162        pub mod RW {
163            #[doc = "OCRAM did not access magic address."]
164            pub const OCRAM_MAM_STATUS_0: u32 = 0;
165            #[doc = "OCRAM accessed magic address."]
166            pub const OCRAM_MAM_STATUS_1: u32 = 0x01;
167        }
168    }
169    #[doc = "ITCM Access Error Status"]
170    pub mod ITCM_ERR_STATUS {
171        pub const offset: u32 = 3;
172        pub const mask: u32 = 0x01 << offset;
173        pub mod R {}
174        pub mod W {}
175        pub mod RW {
176            #[doc = "ITCM access error does not happen"]
177            pub const ITCM_ERR_STATUS_0: u32 = 0;
178            #[doc = "ITCM access error happens."]
179            pub const ITCM_ERR_STATUS_1: u32 = 0x01;
180        }
181    }
182    #[doc = "DTCM Access Error Status"]
183    pub mod DTCM_ERR_STATUS {
184        pub const offset: u32 = 4;
185        pub const mask: u32 = 0x01 << offset;
186        pub mod R {}
187        pub mod W {}
188        pub mod RW {
189            #[doc = "DTCM access error does not happen"]
190            pub const DTCM_ERR_STATUS_0: u32 = 0;
191            #[doc = "DTCM access error happens."]
192            pub const DTCM_ERR_STATUS_1: u32 = 0x01;
193        }
194    }
195    #[doc = "OCRAM Access Error Status"]
196    pub mod OCRAM_ERR_STATUS {
197        pub const offset: u32 = 5;
198        pub const mask: u32 = 0x01 << offset;
199        pub mod R {}
200        pub mod W {}
201        pub mod RW {
202            #[doc = "OCRAM access error does not happen"]
203            pub const OCRAM_ERR_STATUS_0: u32 = 0;
204            #[doc = "OCRAM access error happens."]
205            pub const OCRAM_ERR_STATUS_1: u32 = 0x01;
206        }
207    }
208}
209#[doc = "Interrupt Status Enable Register"]
210pub mod INT_STAT_EN {
211    #[doc = "ITCM Magic Address Match Status Enable"]
212    pub mod ITCM_MAM_STAT_EN {
213        pub const offset: u32 = 0;
214        pub const mask: u32 = 0x01 << offset;
215        pub mod R {}
216        pub mod W {}
217        pub mod RW {
218            #[doc = "Masked"]
219            pub const ITCM_MAM_STAT_EN_0: u32 = 0;
220            #[doc = "Enabled"]
221            pub const ITCM_MAM_STAT_EN_1: u32 = 0x01;
222        }
223    }
224    #[doc = "DTCM Magic Address Match Status Enable"]
225    pub mod DTCM_MAM_STAT_EN {
226        pub const offset: u32 = 1;
227        pub const mask: u32 = 0x01 << offset;
228        pub mod R {}
229        pub mod W {}
230        pub mod RW {
231            #[doc = "Masked"]
232            pub const DTCM_MAM_STAT_EN_0: u32 = 0;
233            #[doc = "Enabled"]
234            pub const DTCM_MAM_STAT_EN_1: u32 = 0x01;
235        }
236    }
237    #[doc = "OCRAM Magic Address Match Status Enable"]
238    pub mod OCRAM_MAM_STAT_EN {
239        pub const offset: u32 = 2;
240        pub const mask: u32 = 0x01 << offset;
241        pub mod R {}
242        pub mod W {}
243        pub mod RW {
244            #[doc = "Masked"]
245            pub const OCRAM_MAM_STAT_EN_0: u32 = 0;
246            #[doc = "Enabled"]
247            pub const OCRAM_MAM_STAT_EN_1: u32 = 0x01;
248        }
249    }
250    #[doc = "ITCM Access Error Status Enable"]
251    pub mod ITCM_ERR_STAT_EN {
252        pub const offset: u32 = 3;
253        pub const mask: u32 = 0x01 << offset;
254        pub mod R {}
255        pub mod W {}
256        pub mod RW {
257            #[doc = "Masked"]
258            pub const ITCM_ERR_STAT_EN_0: u32 = 0;
259            #[doc = "Enabled"]
260            pub const ITCM_ERR_STAT_EN_1: u32 = 0x01;
261        }
262    }
263    #[doc = "DTCM Access Error Status Enable"]
264    pub mod DTCM_ERR_STAT_EN {
265        pub const offset: u32 = 4;
266        pub const mask: u32 = 0x01 << offset;
267        pub mod R {}
268        pub mod W {}
269        pub mod RW {
270            #[doc = "Masked"]
271            pub const DTCM_ERR_STAT_EN_0: u32 = 0;
272            #[doc = "Enabled"]
273            pub const DTCM_ERR_STAT_EN_1: u32 = 0x01;
274        }
275    }
276    #[doc = "OCRAM Access Error Status Enable"]
277    pub mod OCRAM_ERR_STAT_EN {
278        pub const offset: u32 = 5;
279        pub const mask: u32 = 0x01 << offset;
280        pub mod R {}
281        pub mod W {}
282        pub mod RW {
283            #[doc = "Masked"]
284            pub const OCRAM_ERR_STAT_EN_0: u32 = 0;
285            #[doc = "Enabled"]
286            pub const OCRAM_ERR_STAT_EN_1: u32 = 0x01;
287        }
288    }
289}
290#[doc = "Interrupt Enable Register"]
291pub mod INT_SIG_EN {
292    #[doc = "ITCM Magic Address Match Interrupt Enable"]
293    pub mod ITCM_MAM_SIG_EN {
294        pub const offset: u32 = 0;
295        pub const mask: u32 = 0x01 << offset;
296        pub mod R {}
297        pub mod W {}
298        pub mod RW {
299            #[doc = "Masked"]
300            pub const ITCM_MAM_SIG_EN_0: u32 = 0;
301            #[doc = "Enabled"]
302            pub const ITCM_MAM_SIG_EN_1: u32 = 0x01;
303        }
304    }
305    #[doc = "DTCM Magic Address Match Interrupt Enable"]
306    pub mod DTCM_MAM_SIG_EN {
307        pub const offset: u32 = 1;
308        pub const mask: u32 = 0x01 << offset;
309        pub mod R {}
310        pub mod W {}
311        pub mod RW {
312            #[doc = "Masked"]
313            pub const DTCM_MAM_SIG_EN_0: u32 = 0;
314            #[doc = "Enabled"]
315            pub const DTCM_MAM_SIG_EN_1: u32 = 0x01;
316        }
317    }
318    #[doc = "OCRAM Magic Address Match Interrupt Enable"]
319    pub mod OCRAM_MAM_SIG_EN {
320        pub const offset: u32 = 2;
321        pub const mask: u32 = 0x01 << offset;
322        pub mod R {}
323        pub mod W {}
324        pub mod RW {
325            #[doc = "Masked"]
326            pub const OCRAM_MAM_SIG_EN_0: u32 = 0;
327            #[doc = "Enabled"]
328            pub const OCRAM_MAM_SIG_EN_1: u32 = 0x01;
329        }
330    }
331    #[doc = "ITCM Access Error Interrupt Enable"]
332    pub mod ITCM_ERR_SIG_EN {
333        pub const offset: u32 = 3;
334        pub const mask: u32 = 0x01 << offset;
335        pub mod R {}
336        pub mod W {}
337        pub mod RW {
338            #[doc = "Masked"]
339            pub const ITCM_ERR_SIG_EN_0: u32 = 0;
340            #[doc = "Enabled"]
341            pub const ITCM_ERR_SIG_EN_1: u32 = 0x01;
342        }
343    }
344    #[doc = "DTCM Access Error Interrupt Enable"]
345    pub mod DTCM_ERR_SIG_EN {
346        pub const offset: u32 = 4;
347        pub const mask: u32 = 0x01 << offset;
348        pub mod R {}
349        pub mod W {}
350        pub mod RW {
351            #[doc = "Masked"]
352            pub const DTCM_ERR_SIG_EN_0: u32 = 0;
353            #[doc = "Enabled"]
354            pub const DTCM_ERR_SIG_EN_1: u32 = 0x01;
355        }
356    }
357    #[doc = "OCRAM Access Error Interrupt Enable"]
358    pub mod OCRAM_ERR_SIG_EN {
359        pub const offset: u32 = 5;
360        pub const mask: u32 = 0x01 << offset;
361        pub mod R {}
362        pub mod W {}
363        pub mod RW {
364            #[doc = "Masked"]
365            pub const OCRAM_ERR_SIG_EN_0: u32 = 0;
366            #[doc = "Enabled"]
367            pub const OCRAM_ERR_SIG_EN_1: u32 = 0x01;
368        }
369    }
370}
imxrt_ral/blocks/imxrt1011/flexram.rs

imxrt_ral/blocks/imxrt1011/
flexram.rs
