rp2040_pac/pio0/
input_sync_bypass.rs

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1#[doc = "Register `INPUT_SYNC_BYPASS` reader"]
2pub type R = crate::R<INPUT_SYNC_BYPASS_SPEC>;
3#[doc = "Register `INPUT_SYNC_BYPASS` writer"]
4pub type W = crate::W<INPUT_SYNC_BYPASS_SPEC>;
5impl core::fmt::Debug for R {
6    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7        write!(f, "{}", self.bits())
8    }
9}
10impl core::fmt::Debug for crate::generic::Reg<INPUT_SYNC_BYPASS_SPEC> {
11    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
12        core::fmt::Debug::fmt(&self.read(), f)
13    }
14}
15impl W {
16    #[doc = r" Writes raw bits to the register."]
17    #[doc = r""]
18    #[doc = r" # Safety"]
19    #[doc = r""]
20    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
21    #[inline(always)]
22    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
23        self.bits = bits;
24        self
25    }
26}
27#[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.  
28 0 -> input is synchronized (default)  
29 1 -> synchronizer is bypassed  
30 If in doubt, leave this register as all zeroes.  
31
32You can [`read`](crate::generic::Reg::read) this register and get [`input_sync_bypass::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`input_sync_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
33pub struct INPUT_SYNC_BYPASS_SPEC;
34impl crate::RegisterSpec for INPUT_SYNC_BYPASS_SPEC {
35    type Ux = u32;
36}
37#[doc = "`read()` method returns [`input_sync_bypass::R`](R) reader structure"]
38impl crate::Readable for INPUT_SYNC_BYPASS_SPEC {}
39#[doc = "`write(|w| ..)` method takes [`input_sync_bypass::W`](W) writer structure"]
40impl crate::Writable for INPUT_SYNC_BYPASS_SPEC {
41    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets INPUT_SYNC_BYPASS to value 0"]
45impl crate::Resettable for INPUT_SYNC_BYPASS_SPEC {
46    const RESET_VALUE: u32 = 0;
47}
rp2040_pac/pio0/input_sync_bypass.rs

rp2040_pac/pio0/
input_sync_bypass.rs
