imxrt_ral/blocks/imxrt1011/
pmu.rs
1#[doc = "PMU"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x0110],
5 #[doc = "Regulator 1P1 Register"]
6 pub REG_1P1: crate::RWRegister<u32>,
7 #[doc = "Regulator 1P1 Register"]
8 pub REG_1P1_SET: crate::RWRegister<u32>,
9 #[doc = "Regulator 1P1 Register"]
10 pub REG_1P1_CLR: crate::RWRegister<u32>,
11 #[doc = "Regulator 1P1 Register"]
12 pub REG_1P1_TOG: crate::RWRegister<u32>,
13 #[doc = "Regulator 3P0 Register"]
14 pub REG_3P0: crate::RWRegister<u32>,
15 #[doc = "Regulator 3P0 Register"]
16 pub REG_3P0_SET: crate::RWRegister<u32>,
17 #[doc = "Regulator 3P0 Register"]
18 pub REG_3P0_CLR: crate::RWRegister<u32>,
19 #[doc = "Regulator 3P0 Register"]
20 pub REG_3P0_TOG: crate::RWRegister<u32>,
21 #[doc = "Regulator 2P5 Register"]
22 pub REG_2P5: crate::RWRegister<u32>,
23 #[doc = "Regulator 2P5 Register"]
24 pub REG_2P5_SET: crate::RWRegister<u32>,
25 #[doc = "Regulator 2P5 Register"]
26 pub REG_2P5_CLR: crate::RWRegister<u32>,
27 #[doc = "Regulator 2P5 Register"]
28 pub REG_2P5_TOG: crate::RWRegister<u32>,
29 #[doc = "Digital Regulator Core Register"]
30 pub REG_CORE: crate::RWRegister<u32>,
31 #[doc = "Digital Regulator Core Register"]
32 pub REG_CORE_SET: crate::RWRegister<u32>,
33 #[doc = "Digital Regulator Core Register"]
34 pub REG_CORE_CLR: crate::RWRegister<u32>,
35 #[doc = "Digital Regulator Core Register"]
36 pub REG_CORE_TOG: crate::RWRegister<u32>,
37 #[doc = "Miscellaneous Register 0"]
38 pub MISC0: crate::RWRegister<u32>,
39 #[doc = "Miscellaneous Register 0"]
40 pub MISC0_SET: crate::RWRegister<u32>,
41 #[doc = "Miscellaneous Register 0"]
42 pub MISC0_CLR: crate::RWRegister<u32>,
43 #[doc = "Miscellaneous Register 0"]
44 pub MISC0_TOG: crate::RWRegister<u32>,
45 #[doc = "Miscellaneous Register 1"]
46 pub MISC1: crate::RWRegister<u32>,
47 #[doc = "Miscellaneous Register 1"]
48 pub MISC1_SET: crate::RWRegister<u32>,
49 #[doc = "Miscellaneous Register 1"]
50 pub MISC1_CLR: crate::RWRegister<u32>,
51 #[doc = "Miscellaneous Register 1"]
52 pub MISC1_TOG: crate::RWRegister<u32>,
53 #[doc = "Miscellaneous Control Register"]
54 pub MISC2: crate::RWRegister<u32>,
55 #[doc = "Miscellaneous Control Register"]
56 pub MISC2_SET: crate::RWRegister<u32>,
57 #[doc = "Miscellaneous Control Register"]
58 pub MISC2_CLR: crate::RWRegister<u32>,
59 #[doc = "Miscellaneous Control Register"]
60 pub MISC2_TOG: crate::RWRegister<u32>,
61}
62#[doc = "Regulator 1P1 Register"]
63pub mod REG_1P1 {
64 #[doc = "Control bit to enable the regulator output."]
65 pub mod ENABLE_LINREG {
66 pub const offset: u32 = 0;
67 pub const mask: u32 = 0x01 << offset;
68 pub mod R {}
69 pub mod W {}
70 pub mod RW {}
71 }
72 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
73 pub mod ENABLE_BO {
74 pub const offset: u32 = 1;
75 pub const mask: u32 = 0x01 << offset;
76 pub mod R {}
77 pub mod W {}
78 pub mod RW {}
79 }
80 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
81 pub mod ENABLE_ILIMIT {
82 pub const offset: u32 = 2;
83 pub const mask: u32 = 0x01 << offset;
84 pub mod R {}
85 pub mod W {}
86 pub mod RW {}
87 }
88 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
89 pub mod ENABLE_PULLDOWN {
90 pub const offset: u32 = 3;
91 pub const mask: u32 = 0x01 << offset;
92 pub mod R {}
93 pub mod W {}
94 pub mod RW {}
95 }
96 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
97 pub mod BO_OFFSET {
98 pub const offset: u32 = 4;
99 pub const mask: u32 = 0x07 << offset;
100 pub mod R {}
101 pub mod W {}
102 pub mod RW {}
103 }
104 #[doc = "Control bits to adjust the regulator output voltage"]
105 pub mod OUTPUT_TRG {
106 pub const offset: u32 = 8;
107 pub const mask: u32 = 0x1f << offset;
108 pub mod R {}
109 pub mod W {}
110 pub mod RW {
111 #[doc = "0.8V"]
112 pub const OUTPUT_TRG_4: u32 = 0x04;
113 #[doc = "1.1V"]
114 pub const OUTPUT_TRG_16: u32 = 0x10;
115 }
116 }
117 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
118 pub mod BO_VDD1P1 {
119 pub const offset: u32 = 16;
120 pub const mask: u32 = 0x01 << offset;
121 pub mod R {}
122 pub mod W {}
123 pub mod RW {}
124 }
125 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
126 pub mod OK_VDD1P1 {
127 pub const offset: u32 = 17;
128 pub const mask: u32 = 0x01 << offset;
129 pub mod R {}
130 pub mod W {}
131 pub mod RW {}
132 }
133 #[doc = "Enables the weak 1p1 regulator"]
134 pub mod ENABLE_WEAK_LINREG {
135 pub const offset: u32 = 18;
136 pub const mask: u32 = 0x01 << offset;
137 pub mod R {}
138 pub mod W {}
139 pub mod RW {}
140 }
141 #[doc = "Selects the source for the reference voltage of the weak 1p1 regulator."]
142 pub mod SELREF_WEAK_LINREG {
143 pub const offset: u32 = 19;
144 pub const mask: u32 = 0x01 << offset;
145 pub mod R {}
146 pub mod W {}
147 pub mod RW {
148 #[doc = "Weak-linreg output tracks low-power-bandgap voltage"]
149 pub const SELREF_WEAK_LINREG_0: u32 = 0;
150 #[doc = "Weak-linreg output tracks VDD_SOC_IN voltage"]
151 pub const SELREF_WEAK_LINREG_1: u32 = 0x01;
152 }
153 }
154}
155#[doc = "Regulator 1P1 Register"]
156pub mod REG_1P1_SET {
157 #[doc = "Control bit to enable the regulator output."]
158 pub mod ENABLE_LINREG {
159 pub const offset: u32 = 0;
160 pub const mask: u32 = 0x01 << offset;
161 pub mod R {}
162 pub mod W {}
163 pub mod RW {}
164 }
165 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
166 pub mod ENABLE_BO {
167 pub const offset: u32 = 1;
168 pub const mask: u32 = 0x01 << offset;
169 pub mod R {}
170 pub mod W {}
171 pub mod RW {}
172 }
173 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
174 pub mod ENABLE_ILIMIT {
175 pub const offset: u32 = 2;
176 pub const mask: u32 = 0x01 << offset;
177 pub mod R {}
178 pub mod W {}
179 pub mod RW {}
180 }
181 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
182 pub mod ENABLE_PULLDOWN {
183 pub const offset: u32 = 3;
184 pub const mask: u32 = 0x01 << offset;
185 pub mod R {}
186 pub mod W {}
187 pub mod RW {}
188 }
189 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
190 pub mod BO_OFFSET {
191 pub const offset: u32 = 4;
192 pub const mask: u32 = 0x07 << offset;
193 pub mod R {}
194 pub mod W {}
195 pub mod RW {}
196 }
197 #[doc = "Control bits to adjust the regulator output voltage"]
198 pub mod OUTPUT_TRG {
199 pub const offset: u32 = 8;
200 pub const mask: u32 = 0x1f << offset;
201 pub mod R {}
202 pub mod W {}
203 pub mod RW {
204 #[doc = "0.8V"]
205 pub const OUTPUT_TRG_4: u32 = 0x04;
206 #[doc = "1.1V"]
207 pub const OUTPUT_TRG_16: u32 = 0x10;
208 }
209 }
210 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
211 pub mod BO_VDD1P1 {
212 pub const offset: u32 = 16;
213 pub const mask: u32 = 0x01 << offset;
214 pub mod R {}
215 pub mod W {}
216 pub mod RW {}
217 }
218 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
219 pub mod OK_VDD1P1 {
220 pub const offset: u32 = 17;
221 pub const mask: u32 = 0x01 << offset;
222 pub mod R {}
223 pub mod W {}
224 pub mod RW {}
225 }
226 #[doc = "Enables the weak 1p1 regulator"]
227 pub mod ENABLE_WEAK_LINREG {
228 pub const offset: u32 = 18;
229 pub const mask: u32 = 0x01 << offset;
230 pub mod R {}
231 pub mod W {}
232 pub mod RW {}
233 }
234 #[doc = "Selects the source for the reference voltage of the weak 1p1 regulator."]
235 pub mod SELREF_WEAK_LINREG {
236 pub const offset: u32 = 19;
237 pub const mask: u32 = 0x01 << offset;
238 pub mod R {}
239 pub mod W {}
240 pub mod RW {
241 #[doc = "Weak-linreg output tracks low-power-bandgap voltage"]
242 pub const SELREF_WEAK_LINREG_0: u32 = 0;
243 #[doc = "Weak-linreg output tracks VDD_SOC_IN voltage"]
244 pub const SELREF_WEAK_LINREG_1: u32 = 0x01;
245 }
246 }
247}
248#[doc = "Regulator 1P1 Register"]
249pub mod REG_1P1_CLR {
250 #[doc = "Control bit to enable the regulator output."]
251 pub mod ENABLE_LINREG {
252 pub const offset: u32 = 0;
253 pub const mask: u32 = 0x01 << offset;
254 pub mod R {}
255 pub mod W {}
256 pub mod RW {}
257 }
258 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
259 pub mod ENABLE_BO {
260 pub const offset: u32 = 1;
261 pub const mask: u32 = 0x01 << offset;
262 pub mod R {}
263 pub mod W {}
264 pub mod RW {}
265 }
266 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
267 pub mod ENABLE_ILIMIT {
268 pub const offset: u32 = 2;
269 pub const mask: u32 = 0x01 << offset;
270 pub mod R {}
271 pub mod W {}
272 pub mod RW {}
273 }
274 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
275 pub mod ENABLE_PULLDOWN {
276 pub const offset: u32 = 3;
277 pub const mask: u32 = 0x01 << offset;
278 pub mod R {}
279 pub mod W {}
280 pub mod RW {}
281 }
282 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
283 pub mod BO_OFFSET {
284 pub const offset: u32 = 4;
285 pub const mask: u32 = 0x07 << offset;
286 pub mod R {}
287 pub mod W {}
288 pub mod RW {}
289 }
290 #[doc = "Control bits to adjust the regulator output voltage"]
291 pub mod OUTPUT_TRG {
292 pub const offset: u32 = 8;
293 pub const mask: u32 = 0x1f << offset;
294 pub mod R {}
295 pub mod W {}
296 pub mod RW {
297 #[doc = "0.8V"]
298 pub const OUTPUT_TRG_4: u32 = 0x04;
299 #[doc = "1.1V"]
300 pub const OUTPUT_TRG_16: u32 = 0x10;
301 }
302 }
303 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
304 pub mod BO_VDD1P1 {
305 pub const offset: u32 = 16;
306 pub const mask: u32 = 0x01 << offset;
307 pub mod R {}
308 pub mod W {}
309 pub mod RW {}
310 }
311 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
312 pub mod OK_VDD1P1 {
313 pub const offset: u32 = 17;
314 pub const mask: u32 = 0x01 << offset;
315 pub mod R {}
316 pub mod W {}
317 pub mod RW {}
318 }
319 #[doc = "Enables the weak 1p1 regulator"]
320 pub mod ENABLE_WEAK_LINREG {
321 pub const offset: u32 = 18;
322 pub const mask: u32 = 0x01 << offset;
323 pub mod R {}
324 pub mod W {}
325 pub mod RW {}
326 }
327 #[doc = "Selects the source for the reference voltage of the weak 1p1 regulator."]
328 pub mod SELREF_WEAK_LINREG {
329 pub const offset: u32 = 19;
330 pub const mask: u32 = 0x01 << offset;
331 pub mod R {}
332 pub mod W {}
333 pub mod RW {
334 #[doc = "Weak-linreg output tracks low-power-bandgap voltage"]
335 pub const SELREF_WEAK_LINREG_0: u32 = 0;
336 #[doc = "Weak-linreg output tracks VDD_SOC_IN voltage"]
337 pub const SELREF_WEAK_LINREG_1: u32 = 0x01;
338 }
339 }
340}
341#[doc = "Regulator 1P1 Register"]
342pub mod REG_1P1_TOG {
343 #[doc = "Control bit to enable the regulator output."]
344 pub mod ENABLE_LINREG {
345 pub const offset: u32 = 0;
346 pub const mask: u32 = 0x01 << offset;
347 pub mod R {}
348 pub mod W {}
349 pub mod RW {}
350 }
351 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
352 pub mod ENABLE_BO {
353 pub const offset: u32 = 1;
354 pub const mask: u32 = 0x01 << offset;
355 pub mod R {}
356 pub mod W {}
357 pub mod RW {}
358 }
359 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
360 pub mod ENABLE_ILIMIT {
361 pub const offset: u32 = 2;
362 pub const mask: u32 = 0x01 << offset;
363 pub mod R {}
364 pub mod W {}
365 pub mod RW {}
366 }
367 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
368 pub mod ENABLE_PULLDOWN {
369 pub const offset: u32 = 3;
370 pub const mask: u32 = 0x01 << offset;
371 pub mod R {}
372 pub mod W {}
373 pub mod RW {}
374 }
375 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
376 pub mod BO_OFFSET {
377 pub const offset: u32 = 4;
378 pub const mask: u32 = 0x07 << offset;
379 pub mod R {}
380 pub mod W {}
381 pub mod RW {}
382 }
383 #[doc = "Control bits to adjust the regulator output voltage"]
384 pub mod OUTPUT_TRG {
385 pub const offset: u32 = 8;
386 pub const mask: u32 = 0x1f << offset;
387 pub mod R {}
388 pub mod W {}
389 pub mod RW {
390 #[doc = "0.8V"]
391 pub const OUTPUT_TRG_4: u32 = 0x04;
392 #[doc = "1.1V"]
393 pub const OUTPUT_TRG_16: u32 = 0x10;
394 }
395 }
396 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
397 pub mod BO_VDD1P1 {
398 pub const offset: u32 = 16;
399 pub const mask: u32 = 0x01 << offset;
400 pub mod R {}
401 pub mod W {}
402 pub mod RW {}
403 }
404 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
405 pub mod OK_VDD1P1 {
406 pub const offset: u32 = 17;
407 pub const mask: u32 = 0x01 << offset;
408 pub mod R {}
409 pub mod W {}
410 pub mod RW {}
411 }
412 #[doc = "Enables the weak 1p1 regulator"]
413 pub mod ENABLE_WEAK_LINREG {
414 pub const offset: u32 = 18;
415 pub const mask: u32 = 0x01 << offset;
416 pub mod R {}
417 pub mod W {}
418 pub mod RW {}
419 }
420 #[doc = "Selects the source for the reference voltage of the weak 1p1 regulator."]
421 pub mod SELREF_WEAK_LINREG {
422 pub const offset: u32 = 19;
423 pub const mask: u32 = 0x01 << offset;
424 pub mod R {}
425 pub mod W {}
426 pub mod RW {
427 #[doc = "Weak-linreg output tracks low-power-bandgap voltage"]
428 pub const SELREF_WEAK_LINREG_0: u32 = 0;
429 #[doc = "Weak-linreg output tracks VDD_SOC_IN voltage"]
430 pub const SELREF_WEAK_LINREG_1: u32 = 0x01;
431 }
432 }
433}
434#[doc = "Regulator 3P0 Register"]
435pub mod REG_3P0 {
436 #[doc = "Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference"]
437 pub mod ENABLE_LINREG {
438 pub const offset: u32 = 0;
439 pub const mask: u32 = 0x01 << offset;
440 pub mod R {}
441 pub mod W {}
442 pub mod RW {}
443 }
444 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
445 pub mod ENABLE_BO {
446 pub const offset: u32 = 1;
447 pub const mask: u32 = 0x01 << offset;
448 pub mod R {}
449 pub mod W {}
450 pub mod RW {}
451 }
452 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
453 pub mod ENABLE_ILIMIT {
454 pub const offset: u32 = 2;
455 pub const mask: u32 = 0x01 << offset;
456 pub mod R {}
457 pub mod W {}
458 pub mod RW {}
459 }
460 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
461 pub mod BO_OFFSET {
462 pub const offset: u32 = 4;
463 pub const mask: u32 = 0x07 << offset;
464 pub mod R {}
465 pub mod W {}
466 pub mod RW {}
467 }
468 #[doc = "Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS"]
469 pub mod VBUS_SEL {
470 pub const offset: u32 = 7;
471 pub const mask: u32 = 0x01 << offset;
472 pub mod R {}
473 pub mod W {}
474 pub mod RW {
475 #[doc = "Utilize VBUS OTG2 power"]
476 pub const USB_OTG2_VBUS: u32 = 0;
477 #[doc = "Utilize VBUS OTG1 power"]
478 pub const USB_OTG1_VBUS: u32 = 0x01;
479 }
480 }
481 #[doc = "Control bits to adjust the regulator output voltage"]
482 pub mod OUTPUT_TRG {
483 pub const offset: u32 = 8;
484 pub const mask: u32 = 0x1f << offset;
485 pub mod R {}
486 pub mod W {}
487 pub mod RW {
488 #[doc = "2.625V"]
489 pub const OUTPUT_TRG_0: u32 = 0;
490 #[doc = "3.000V"]
491 pub const OUTPUT_TRG_15: u32 = 0x0f;
492 #[doc = "3.400V"]
493 pub const OUTPUT_TRG_31: u32 = 0x1f;
494 }
495 }
496 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
497 pub mod BO_VDD3P0 {
498 pub const offset: u32 = 16;
499 pub const mask: u32 = 0x01 << offset;
500 pub mod R {}
501 pub mod W {}
502 pub mod RW {}
503 }
504 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
505 pub mod OK_VDD3P0 {
506 pub const offset: u32 = 17;
507 pub const mask: u32 = 0x01 << offset;
508 pub mod R {}
509 pub mod W {}
510 pub mod RW {}
511 }
512}
513#[doc = "Regulator 3P0 Register"]
514pub mod REG_3P0_SET {
515 #[doc = "Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference"]
516 pub mod ENABLE_LINREG {
517 pub const offset: u32 = 0;
518 pub const mask: u32 = 0x01 << offset;
519 pub mod R {}
520 pub mod W {}
521 pub mod RW {}
522 }
523 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
524 pub mod ENABLE_BO {
525 pub const offset: u32 = 1;
526 pub const mask: u32 = 0x01 << offset;
527 pub mod R {}
528 pub mod W {}
529 pub mod RW {}
530 }
531 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
532 pub mod ENABLE_ILIMIT {
533 pub const offset: u32 = 2;
534 pub const mask: u32 = 0x01 << offset;
535 pub mod R {}
536 pub mod W {}
537 pub mod RW {}
538 }
539 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
540 pub mod BO_OFFSET {
541 pub const offset: u32 = 4;
542 pub const mask: u32 = 0x07 << offset;
543 pub mod R {}
544 pub mod W {}
545 pub mod RW {}
546 }
547 #[doc = "Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS"]
548 pub mod VBUS_SEL {
549 pub const offset: u32 = 7;
550 pub const mask: u32 = 0x01 << offset;
551 pub mod R {}
552 pub mod W {}
553 pub mod RW {
554 #[doc = "Utilize VBUS OTG2 power"]
555 pub const USB_OTG2_VBUS: u32 = 0;
556 #[doc = "Utilize VBUS OTG1 power"]
557 pub const USB_OTG1_VBUS: u32 = 0x01;
558 }
559 }
560 #[doc = "Control bits to adjust the regulator output voltage"]
561 pub mod OUTPUT_TRG {
562 pub const offset: u32 = 8;
563 pub const mask: u32 = 0x1f << offset;
564 pub mod R {}
565 pub mod W {}
566 pub mod RW {
567 #[doc = "2.625V"]
568 pub const OUTPUT_TRG_0: u32 = 0;
569 #[doc = "3.000V"]
570 pub const OUTPUT_TRG_15: u32 = 0x0f;
571 #[doc = "3.400V"]
572 pub const OUTPUT_TRG_31: u32 = 0x1f;
573 }
574 }
575 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
576 pub mod BO_VDD3P0 {
577 pub const offset: u32 = 16;
578 pub const mask: u32 = 0x01 << offset;
579 pub mod R {}
580 pub mod W {}
581 pub mod RW {}
582 }
583 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
584 pub mod OK_VDD3P0 {
585 pub const offset: u32 = 17;
586 pub const mask: u32 = 0x01 << offset;
587 pub mod R {}
588 pub mod W {}
589 pub mod RW {}
590 }
591}
592#[doc = "Regulator 3P0 Register"]
593pub mod REG_3P0_CLR {
594 #[doc = "Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference"]
595 pub mod ENABLE_LINREG {
596 pub const offset: u32 = 0;
597 pub const mask: u32 = 0x01 << offset;
598 pub mod R {}
599 pub mod W {}
600 pub mod RW {}
601 }
602 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
603 pub mod ENABLE_BO {
604 pub const offset: u32 = 1;
605 pub const mask: u32 = 0x01 << offset;
606 pub mod R {}
607 pub mod W {}
608 pub mod RW {}
609 }
610 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
611 pub mod ENABLE_ILIMIT {
612 pub const offset: u32 = 2;
613 pub const mask: u32 = 0x01 << offset;
614 pub mod R {}
615 pub mod W {}
616 pub mod RW {}
617 }
618 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
619 pub mod BO_OFFSET {
620 pub const offset: u32 = 4;
621 pub const mask: u32 = 0x07 << offset;
622 pub mod R {}
623 pub mod W {}
624 pub mod RW {}
625 }
626 #[doc = "Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS"]
627 pub mod VBUS_SEL {
628 pub const offset: u32 = 7;
629 pub const mask: u32 = 0x01 << offset;
630 pub mod R {}
631 pub mod W {}
632 pub mod RW {
633 #[doc = "Utilize VBUS OTG2 power"]
634 pub const USB_OTG2_VBUS: u32 = 0;
635 #[doc = "Utilize VBUS OTG1 power"]
636 pub const USB_OTG1_VBUS: u32 = 0x01;
637 }
638 }
639 #[doc = "Control bits to adjust the regulator output voltage"]
640 pub mod OUTPUT_TRG {
641 pub const offset: u32 = 8;
642 pub const mask: u32 = 0x1f << offset;
643 pub mod R {}
644 pub mod W {}
645 pub mod RW {
646 #[doc = "2.625V"]
647 pub const OUTPUT_TRG_0: u32 = 0;
648 #[doc = "3.000V"]
649 pub const OUTPUT_TRG_15: u32 = 0x0f;
650 #[doc = "3.400V"]
651 pub const OUTPUT_TRG_31: u32 = 0x1f;
652 }
653 }
654 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
655 pub mod BO_VDD3P0 {
656 pub const offset: u32 = 16;
657 pub const mask: u32 = 0x01 << offset;
658 pub mod R {}
659 pub mod W {}
660 pub mod RW {}
661 }
662 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
663 pub mod OK_VDD3P0 {
664 pub const offset: u32 = 17;
665 pub const mask: u32 = 0x01 << offset;
666 pub mod R {}
667 pub mod W {}
668 pub mod RW {}
669 }
670}
671#[doc = "Regulator 3P0 Register"]
672pub mod REG_3P0_TOG {
673 #[doc = "Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference"]
674 pub mod ENABLE_LINREG {
675 pub const offset: u32 = 0;
676 pub const mask: u32 = 0x01 << offset;
677 pub mod R {}
678 pub mod W {}
679 pub mod RW {}
680 }
681 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
682 pub mod ENABLE_BO {
683 pub const offset: u32 = 1;
684 pub const mask: u32 = 0x01 << offset;
685 pub mod R {}
686 pub mod W {}
687 pub mod RW {}
688 }
689 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
690 pub mod ENABLE_ILIMIT {
691 pub const offset: u32 = 2;
692 pub const mask: u32 = 0x01 << offset;
693 pub mod R {}
694 pub mod W {}
695 pub mod RW {}
696 }
697 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
698 pub mod BO_OFFSET {
699 pub const offset: u32 = 4;
700 pub const mask: u32 = 0x07 << offset;
701 pub mod R {}
702 pub mod W {}
703 pub mod RW {}
704 }
705 #[doc = "Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS"]
706 pub mod VBUS_SEL {
707 pub const offset: u32 = 7;
708 pub const mask: u32 = 0x01 << offset;
709 pub mod R {}
710 pub mod W {}
711 pub mod RW {
712 #[doc = "Utilize VBUS OTG2 power"]
713 pub const USB_OTG2_VBUS: u32 = 0;
714 #[doc = "Utilize VBUS OTG1 power"]
715 pub const USB_OTG1_VBUS: u32 = 0x01;
716 }
717 }
718 #[doc = "Control bits to adjust the regulator output voltage"]
719 pub mod OUTPUT_TRG {
720 pub const offset: u32 = 8;
721 pub const mask: u32 = 0x1f << offset;
722 pub mod R {}
723 pub mod W {}
724 pub mod RW {
725 #[doc = "2.625V"]
726 pub const OUTPUT_TRG_0: u32 = 0;
727 #[doc = "3.000V"]
728 pub const OUTPUT_TRG_15: u32 = 0x0f;
729 #[doc = "3.400V"]
730 pub const OUTPUT_TRG_31: u32 = 0x1f;
731 }
732 }
733 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
734 pub mod BO_VDD3P0 {
735 pub const offset: u32 = 16;
736 pub const mask: u32 = 0x01 << offset;
737 pub mod R {}
738 pub mod W {}
739 pub mod RW {}
740 }
741 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
742 pub mod OK_VDD3P0 {
743 pub const offset: u32 = 17;
744 pub const mask: u32 = 0x01 << offset;
745 pub mod R {}
746 pub mod W {}
747 pub mod RW {}
748 }
749}
750#[doc = "Regulator 2P5 Register"]
751pub mod REG_2P5 {
752 #[doc = "Control bit to enable the regulator output."]
753 pub mod ENABLE_LINREG {
754 pub const offset: u32 = 0;
755 pub const mask: u32 = 0x01 << offset;
756 pub mod R {}
757 pub mod W {}
758 pub mod RW {}
759 }
760 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
761 pub mod ENABLE_BO {
762 pub const offset: u32 = 1;
763 pub const mask: u32 = 0x01 << offset;
764 pub mod R {}
765 pub mod W {}
766 pub mod RW {}
767 }
768 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
769 pub mod ENABLE_ILIMIT {
770 pub const offset: u32 = 2;
771 pub const mask: u32 = 0x01 << offset;
772 pub mod R {}
773 pub mod W {}
774 pub mod RW {}
775 }
776 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
777 pub mod ENABLE_PULLDOWN {
778 pub const offset: u32 = 3;
779 pub const mask: u32 = 0x01 << offset;
780 pub mod R {}
781 pub mod W {}
782 pub mod RW {}
783 }
784 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
785 pub mod BO_OFFSET {
786 pub const offset: u32 = 4;
787 pub const mask: u32 = 0x07 << offset;
788 pub mod R {}
789 pub mod W {}
790 pub mod RW {}
791 }
792 #[doc = "Control bits to adjust the regulator output voltage"]
793 pub mod OUTPUT_TRG {
794 pub const offset: u32 = 8;
795 pub const mask: u32 = 0x1f << offset;
796 pub mod R {}
797 pub mod W {}
798 pub mod RW {
799 #[doc = "2.10V"]
800 pub const OUTPUT_TRG_0: u32 = 0;
801 #[doc = "2.50V"]
802 pub const OUTPUT_TRG_16: u32 = 0x10;
803 #[doc = "2.875V"]
804 pub const OUTPUT_TRG_31: u32 = 0x1f;
805 }
806 }
807 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
808 pub mod BO_VDD2P5 {
809 pub const offset: u32 = 16;
810 pub const mask: u32 = 0x01 << offset;
811 pub mod R {}
812 pub mod W {}
813 pub mod RW {}
814 }
815 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
816 pub mod OK_VDD2P5 {
817 pub const offset: u32 = 17;
818 pub const mask: u32 = 0x01 << offset;
819 pub mod R {}
820 pub mod W {}
821 pub mod RW {}
822 }
823 #[doc = "Enables the weak 2p5 regulator"]
824 pub mod ENABLE_WEAK_LINREG {
825 pub const offset: u32 = 18;
826 pub const mask: u32 = 0x01 << offset;
827 pub mod R {}
828 pub mod W {}
829 pub mod RW {}
830 }
831}
832#[doc = "Regulator 2P5 Register"]
833pub mod REG_2P5_SET {
834 #[doc = "Control bit to enable the regulator output."]
835 pub mod ENABLE_LINREG {
836 pub const offset: u32 = 0;
837 pub const mask: u32 = 0x01 << offset;
838 pub mod R {}
839 pub mod W {}
840 pub mod RW {}
841 }
842 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
843 pub mod ENABLE_BO {
844 pub const offset: u32 = 1;
845 pub const mask: u32 = 0x01 << offset;
846 pub mod R {}
847 pub mod W {}
848 pub mod RW {}
849 }
850 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
851 pub mod ENABLE_ILIMIT {
852 pub const offset: u32 = 2;
853 pub const mask: u32 = 0x01 << offset;
854 pub mod R {}
855 pub mod W {}
856 pub mod RW {}
857 }
858 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
859 pub mod ENABLE_PULLDOWN {
860 pub const offset: u32 = 3;
861 pub const mask: u32 = 0x01 << offset;
862 pub mod R {}
863 pub mod W {}
864 pub mod RW {}
865 }
866 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
867 pub mod BO_OFFSET {
868 pub const offset: u32 = 4;
869 pub const mask: u32 = 0x07 << offset;
870 pub mod R {}
871 pub mod W {}
872 pub mod RW {}
873 }
874 #[doc = "Control bits to adjust the regulator output voltage"]
875 pub mod OUTPUT_TRG {
876 pub const offset: u32 = 8;
877 pub const mask: u32 = 0x1f << offset;
878 pub mod R {}
879 pub mod W {}
880 pub mod RW {
881 #[doc = "2.10V"]
882 pub const OUTPUT_TRG_0: u32 = 0;
883 #[doc = "2.50V"]
884 pub const OUTPUT_TRG_16: u32 = 0x10;
885 #[doc = "2.875V"]
886 pub const OUTPUT_TRG_31: u32 = 0x1f;
887 }
888 }
889 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
890 pub mod BO_VDD2P5 {
891 pub const offset: u32 = 16;
892 pub const mask: u32 = 0x01 << offset;
893 pub mod R {}
894 pub mod W {}
895 pub mod RW {}
896 }
897 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
898 pub mod OK_VDD2P5 {
899 pub const offset: u32 = 17;
900 pub const mask: u32 = 0x01 << offset;
901 pub mod R {}
902 pub mod W {}
903 pub mod RW {}
904 }
905 #[doc = "Enables the weak 2p5 regulator"]
906 pub mod ENABLE_WEAK_LINREG {
907 pub const offset: u32 = 18;
908 pub const mask: u32 = 0x01 << offset;
909 pub mod R {}
910 pub mod W {}
911 pub mod RW {}
912 }
913}
914#[doc = "Regulator 2P5 Register"]
915pub mod REG_2P5_CLR {
916 #[doc = "Control bit to enable the regulator output."]
917 pub mod ENABLE_LINREG {
918 pub const offset: u32 = 0;
919 pub const mask: u32 = 0x01 << offset;
920 pub mod R {}
921 pub mod W {}
922 pub mod RW {}
923 }
924 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
925 pub mod ENABLE_BO {
926 pub const offset: u32 = 1;
927 pub const mask: u32 = 0x01 << offset;
928 pub mod R {}
929 pub mod W {}
930 pub mod RW {}
931 }
932 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
933 pub mod ENABLE_ILIMIT {
934 pub const offset: u32 = 2;
935 pub const mask: u32 = 0x01 << offset;
936 pub mod R {}
937 pub mod W {}
938 pub mod RW {}
939 }
940 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
941 pub mod ENABLE_PULLDOWN {
942 pub const offset: u32 = 3;
943 pub const mask: u32 = 0x01 << offset;
944 pub mod R {}
945 pub mod W {}
946 pub mod RW {}
947 }
948 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
949 pub mod BO_OFFSET {
950 pub const offset: u32 = 4;
951 pub const mask: u32 = 0x07 << offset;
952 pub mod R {}
953 pub mod W {}
954 pub mod RW {}
955 }
956 #[doc = "Control bits to adjust the regulator output voltage"]
957 pub mod OUTPUT_TRG {
958 pub const offset: u32 = 8;
959 pub const mask: u32 = 0x1f << offset;
960 pub mod R {}
961 pub mod W {}
962 pub mod RW {
963 #[doc = "2.10V"]
964 pub const OUTPUT_TRG_0: u32 = 0;
965 #[doc = "2.50V"]
966 pub const OUTPUT_TRG_16: u32 = 0x10;
967 #[doc = "2.875V"]
968 pub const OUTPUT_TRG_31: u32 = 0x1f;
969 }
970 }
971 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
972 pub mod BO_VDD2P5 {
973 pub const offset: u32 = 16;
974 pub const mask: u32 = 0x01 << offset;
975 pub mod R {}
976 pub mod W {}
977 pub mod RW {}
978 }
979 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
980 pub mod OK_VDD2P5 {
981 pub const offset: u32 = 17;
982 pub const mask: u32 = 0x01 << offset;
983 pub mod R {}
984 pub mod W {}
985 pub mod RW {}
986 }
987 #[doc = "Enables the weak 2p5 regulator"]
988 pub mod ENABLE_WEAK_LINREG {
989 pub const offset: u32 = 18;
990 pub const mask: u32 = 0x01 << offset;
991 pub mod R {}
992 pub mod W {}
993 pub mod RW {}
994 }
995}
996#[doc = "Regulator 2P5 Register"]
997pub mod REG_2P5_TOG {
998 #[doc = "Control bit to enable the regulator output."]
999 pub mod ENABLE_LINREG {
1000 pub const offset: u32 = 0;
1001 pub const mask: u32 = 0x01 << offset;
1002 pub mod R {}
1003 pub mod W {}
1004 pub mod RW {}
1005 }
1006 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
1007 pub mod ENABLE_BO {
1008 pub const offset: u32 = 1;
1009 pub const mask: u32 = 0x01 << offset;
1010 pub mod R {}
1011 pub mod W {}
1012 pub mod RW {}
1013 }
1014 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
1015 pub mod ENABLE_ILIMIT {
1016 pub const offset: u32 = 2;
1017 pub const mask: u32 = 0x01 << offset;
1018 pub mod R {}
1019 pub mod W {}
1020 pub mod RW {}
1021 }
1022 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
1023 pub mod ENABLE_PULLDOWN {
1024 pub const offset: u32 = 3;
1025 pub const mask: u32 = 0x01 << offset;
1026 pub mod R {}
1027 pub mod W {}
1028 pub mod RW {}
1029 }
1030 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
1031 pub mod BO_OFFSET {
1032 pub const offset: u32 = 4;
1033 pub const mask: u32 = 0x07 << offset;
1034 pub mod R {}
1035 pub mod W {}
1036 pub mod RW {}
1037 }
1038 #[doc = "Control bits to adjust the regulator output voltage"]
1039 pub mod OUTPUT_TRG {
1040 pub const offset: u32 = 8;
1041 pub const mask: u32 = 0x1f << offset;
1042 pub mod R {}
1043 pub mod W {}
1044 pub mod RW {
1045 #[doc = "2.10V"]
1046 pub const OUTPUT_TRG_0: u32 = 0;
1047 #[doc = "2.50V"]
1048 pub const OUTPUT_TRG_16: u32 = 0x10;
1049 #[doc = "2.875V"]
1050 pub const OUTPUT_TRG_31: u32 = 0x1f;
1051 }
1052 }
1053 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
1054 pub mod BO_VDD2P5 {
1055 pub const offset: u32 = 16;
1056 pub const mask: u32 = 0x01 << offset;
1057 pub mod R {}
1058 pub mod W {}
1059 pub mod RW {}
1060 }
1061 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
1062 pub mod OK_VDD2P5 {
1063 pub const offset: u32 = 17;
1064 pub const mask: u32 = 0x01 << offset;
1065 pub mod R {}
1066 pub mod W {}
1067 pub mod RW {}
1068 }
1069 #[doc = "Enables the weak 2p5 regulator"]
1070 pub mod ENABLE_WEAK_LINREG {
1071 pub const offset: u32 = 18;
1072 pub const mask: u32 = 0x01 << offset;
1073 pub mod R {}
1074 pub mod W {}
1075 pub mod RW {}
1076 }
1077}
1078#[doc = "Digital Regulator Core Register"]
1079pub mod REG_CORE {
1080 #[doc = "This field defines the target voltage for the ARM core power domain"]
1081 pub mod REG0_TARG {
1082 pub const offset: u32 = 0;
1083 pub const mask: u32 = 0x1f << offset;
1084 pub mod R {}
1085 pub mod W {}
1086 pub mod RW {
1087 #[doc = "Power gated off"]
1088 pub const REG0_TARG_0: u32 = 0;
1089 #[doc = "Target core voltage = 0.725V"]
1090 pub const REG0_TARG_1: u32 = 0x01;
1091 #[doc = "Target core voltage = 0.750V"]
1092 pub const REG0_TARG_2: u32 = 0x02;
1093 #[doc = "Target core voltage = 0.775V"]
1094 pub const REG0_TARG_3: u32 = 0x03;
1095 #[doc = "Target core voltage = 1.100V"]
1096 pub const REG0_TARG_16: u32 = 0x10;
1097 #[doc = "Target core voltage = 1.450V"]
1098 pub const REG0_TARG_30: u32 = 0x1e;
1099 #[doc = "Power FET switched full on. No regulation."]
1100 pub const REG0_TARG_31: u32 = 0x1f;
1101 }
1102 }
1103 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1104 pub mod REG0_ADJ {
1105 pub const offset: u32 = 5;
1106 pub const mask: u32 = 0x0f << offset;
1107 pub mod R {}
1108 pub mod W {}
1109 pub mod RW {
1110 #[doc = "No adjustment"]
1111 pub const REG0_ADJ_0: u32 = 0;
1112 #[doc = "+ 0.25%"]
1113 pub const REG0_ADJ_1: u32 = 0x01;
1114 #[doc = "+ 0.50%"]
1115 pub const REG0_ADJ_2: u32 = 0x02;
1116 #[doc = "+ 0.75%"]
1117 pub const REG0_ADJ_3: u32 = 0x03;
1118 #[doc = "+ 1.00%"]
1119 pub const REG0_ADJ_4: u32 = 0x04;
1120 #[doc = "+ 1.25%"]
1121 pub const REG0_ADJ_5: u32 = 0x05;
1122 #[doc = "+ 1.50%"]
1123 pub const REG0_ADJ_6: u32 = 0x06;
1124 #[doc = "+ 1.75%"]
1125 pub const REG0_ADJ_7: u32 = 0x07;
1126 #[doc = "- 0.25%"]
1127 pub const REG0_ADJ_8: u32 = 0x08;
1128 #[doc = "- 0.50%"]
1129 pub const REG0_ADJ_9: u32 = 0x09;
1130 #[doc = "- 0.75%"]
1131 pub const REG0_ADJ_10: u32 = 0x0a;
1132 #[doc = "- 1.00%"]
1133 pub const REG0_ADJ_11: u32 = 0x0b;
1134 #[doc = "- 1.25%"]
1135 pub const REG0_ADJ_12: u32 = 0x0c;
1136 #[doc = "- 1.50%"]
1137 pub const REG0_ADJ_13: u32 = 0x0d;
1138 #[doc = "- 1.75%"]
1139 pub const REG0_ADJ_14: u32 = 0x0e;
1140 #[doc = "- 2.00%"]
1141 pub const REG0_ADJ_15: u32 = 0x0f;
1142 }
1143 }
1144 #[doc = "This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation."]
1145 pub mod REG1_TARG {
1146 pub const offset: u32 = 9;
1147 pub const mask: u32 = 0x1f << offset;
1148 pub mod R {}
1149 pub mod W {}
1150 pub mod RW {
1151 #[doc = "Power gated off"]
1152 pub const REG1_TARG_0: u32 = 0;
1153 #[doc = "Target core voltage = 0.725V"]
1154 pub const REG1_TARG_1: u32 = 0x01;
1155 #[doc = "Target core voltage = 0.750V"]
1156 pub const REG1_TARG_2: u32 = 0x02;
1157 #[doc = "Target core voltage = 0.775V"]
1158 pub const REG1_TARG_3: u32 = 0x03;
1159 #[doc = "Target core voltage = 1.100V"]
1160 pub const REG1_TARG_16: u32 = 0x10;
1161 #[doc = "Target core voltage = 1.450V"]
1162 pub const REG1_TARG_30: u32 = 0x1e;
1163 #[doc = "Power FET switched full on. No regulation."]
1164 pub const REG1_TARG_31: u32 = 0x1f;
1165 }
1166 }
1167 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1168 pub mod REG1_ADJ {
1169 pub const offset: u32 = 14;
1170 pub const mask: u32 = 0x0f << offset;
1171 pub mod R {}
1172 pub mod W {}
1173 pub mod RW {
1174 #[doc = "No adjustment"]
1175 pub const REG1_ADJ_0: u32 = 0;
1176 #[doc = "+ 0.25%"]
1177 pub const REG1_ADJ_1: u32 = 0x01;
1178 #[doc = "+ 0.50%"]
1179 pub const REG1_ADJ_2: u32 = 0x02;
1180 #[doc = "+ 0.75%"]
1181 pub const REG1_ADJ_3: u32 = 0x03;
1182 #[doc = "+ 1.00%"]
1183 pub const REG1_ADJ_4: u32 = 0x04;
1184 #[doc = "+ 1.25%"]
1185 pub const REG1_ADJ_5: u32 = 0x05;
1186 #[doc = "+ 1.50%"]
1187 pub const REG1_ADJ_6: u32 = 0x06;
1188 #[doc = "+ 1.75%"]
1189 pub const REG1_ADJ_7: u32 = 0x07;
1190 #[doc = "- 0.25%"]
1191 pub const REG1_ADJ_8: u32 = 0x08;
1192 #[doc = "- 0.50%"]
1193 pub const REG1_ADJ_9: u32 = 0x09;
1194 #[doc = "- 0.75%"]
1195 pub const REG1_ADJ_10: u32 = 0x0a;
1196 #[doc = "- 1.00%"]
1197 pub const REG1_ADJ_11: u32 = 0x0b;
1198 #[doc = "- 1.25%"]
1199 pub const REG1_ADJ_12: u32 = 0x0c;
1200 #[doc = "- 1.50%"]
1201 pub const REG1_ADJ_13: u32 = 0x0d;
1202 #[doc = "- 1.75%"]
1203 pub const REG1_ADJ_14: u32 = 0x0e;
1204 #[doc = "- 2.00%"]
1205 pub const REG1_ADJ_15: u32 = 0x0f;
1206 }
1207 }
1208 #[doc = "This field defines the target voltage for the SOC power domain"]
1209 pub mod REG2_TARG {
1210 pub const offset: u32 = 18;
1211 pub const mask: u32 = 0x1f << offset;
1212 pub mod R {}
1213 pub mod W {}
1214 pub mod RW {
1215 #[doc = "Power gated off"]
1216 pub const REG2_TARG_0: u32 = 0;
1217 #[doc = "Target core voltage = 0.725V"]
1218 pub const REG2_TARG_1: u32 = 0x01;
1219 #[doc = "Target core voltage = 0.750V"]
1220 pub const REG2_TARG_2: u32 = 0x02;
1221 #[doc = "Target core voltage = 0.775V"]
1222 pub const REG2_TARG_3: u32 = 0x03;
1223 #[doc = "Target core voltage = 1.100V"]
1224 pub const REG2_TARG_16: u32 = 0x10;
1225 #[doc = "Target core voltage = 1.450V"]
1226 pub const REG2_TARG_30: u32 = 0x1e;
1227 #[doc = "Power FET switched full on. No regulation."]
1228 pub const REG2_TARG_31: u32 = 0x1f;
1229 }
1230 }
1231 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1232 pub mod REG2_ADJ {
1233 pub const offset: u32 = 23;
1234 pub const mask: u32 = 0x0f << offset;
1235 pub mod R {}
1236 pub mod W {}
1237 pub mod RW {
1238 #[doc = "No adjustment"]
1239 pub const REG2_ADJ_0: u32 = 0;
1240 #[doc = "+ 0.25%"]
1241 pub const REG2_ADJ_1: u32 = 0x01;
1242 #[doc = "+ 0.50%"]
1243 pub const REG2_ADJ_2: u32 = 0x02;
1244 #[doc = "+ 0.75%"]
1245 pub const REG2_ADJ_3: u32 = 0x03;
1246 #[doc = "+ 1.00%"]
1247 pub const REG2_ADJ_4: u32 = 0x04;
1248 #[doc = "+ 1.25%"]
1249 pub const REG2_ADJ_5: u32 = 0x05;
1250 #[doc = "+ 1.50%"]
1251 pub const REG2_ADJ_6: u32 = 0x06;
1252 #[doc = "+ 1.75%"]
1253 pub const REG2_ADJ_7: u32 = 0x07;
1254 #[doc = "- 0.25%"]
1255 pub const REG2_ADJ_8: u32 = 0x08;
1256 #[doc = "- 0.50%"]
1257 pub const REG2_ADJ_9: u32 = 0x09;
1258 #[doc = "- 0.75%"]
1259 pub const REG2_ADJ_10: u32 = 0x0a;
1260 #[doc = "- 1.00%"]
1261 pub const REG2_ADJ_11: u32 = 0x0b;
1262 #[doc = "- 1.25%"]
1263 pub const REG2_ADJ_12: u32 = 0x0c;
1264 #[doc = "- 1.50%"]
1265 pub const REG2_ADJ_13: u32 = 0x0d;
1266 #[doc = "- 1.75%"]
1267 pub const REG2_ADJ_14: u32 = 0x0e;
1268 #[doc = "- 2.00%"]
1269 pub const REG2_ADJ_15: u32 = 0x0f;
1270 }
1271 }
1272 #[doc = "Regulator voltage ramp rate."]
1273 pub mod RAMP_RATE {
1274 pub const offset: u32 = 27;
1275 pub const mask: u32 = 0x03 << offset;
1276 pub mod R {}
1277 pub mod W {}
1278 pub mod RW {
1279 #[doc = "Fast"]
1280 pub const RAMP_RATE_0: u32 = 0;
1281 #[doc = "Medium Fast"]
1282 pub const RAMP_RATE_1: u32 = 0x01;
1283 #[doc = "Medium Slow"]
1284 pub const RAMP_RATE_2: u32 = 0x02;
1285 #[doc = "Slow"]
1286 pub const RAMP_RATE_3: u32 = 0x03;
1287 }
1288 }
1289 #[doc = "If set, increases the gate drive on power gating FETs to reduce leakage in the off state"]
1290 pub mod FET_ODRIVE {
1291 pub const offset: u32 = 29;
1292 pub const mask: u32 = 0x01 << offset;
1293 pub mod R {}
1294 pub mod W {}
1295 pub mod RW {}
1296 }
1297}
1298#[doc = "Digital Regulator Core Register"]
1299pub mod REG_CORE_SET {
1300 #[doc = "This field defines the target voltage for the ARM core power domain"]
1301 pub mod REG0_TARG {
1302 pub const offset: u32 = 0;
1303 pub const mask: u32 = 0x1f << offset;
1304 pub mod R {}
1305 pub mod W {}
1306 pub mod RW {
1307 #[doc = "Power gated off"]
1308 pub const REG0_TARG_0: u32 = 0;
1309 #[doc = "Target core voltage = 0.725V"]
1310 pub const REG0_TARG_1: u32 = 0x01;
1311 #[doc = "Target core voltage = 0.750V"]
1312 pub const REG0_TARG_2: u32 = 0x02;
1313 #[doc = "Target core voltage = 0.775V"]
1314 pub const REG0_TARG_3: u32 = 0x03;
1315 #[doc = "Target core voltage = 1.100V"]
1316 pub const REG0_TARG_16: u32 = 0x10;
1317 #[doc = "Target core voltage = 1.450V"]
1318 pub const REG0_TARG_30: u32 = 0x1e;
1319 #[doc = "Power FET switched full on. No regulation."]
1320 pub const REG0_TARG_31: u32 = 0x1f;
1321 }
1322 }
1323 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1324 pub mod REG0_ADJ {
1325 pub const offset: u32 = 5;
1326 pub const mask: u32 = 0x0f << offset;
1327 pub mod R {}
1328 pub mod W {}
1329 pub mod RW {
1330 #[doc = "No adjustment"]
1331 pub const REG0_ADJ_0: u32 = 0;
1332 #[doc = "+ 0.25%"]
1333 pub const REG0_ADJ_1: u32 = 0x01;
1334 #[doc = "+ 0.50%"]
1335 pub const REG0_ADJ_2: u32 = 0x02;
1336 #[doc = "+ 0.75%"]
1337 pub const REG0_ADJ_3: u32 = 0x03;
1338 #[doc = "+ 1.00%"]
1339 pub const REG0_ADJ_4: u32 = 0x04;
1340 #[doc = "+ 1.25%"]
1341 pub const REG0_ADJ_5: u32 = 0x05;
1342 #[doc = "+ 1.50%"]
1343 pub const REG0_ADJ_6: u32 = 0x06;
1344 #[doc = "+ 1.75%"]
1345 pub const REG0_ADJ_7: u32 = 0x07;
1346 #[doc = "- 0.25%"]
1347 pub const REG0_ADJ_8: u32 = 0x08;
1348 #[doc = "- 0.50%"]
1349 pub const REG0_ADJ_9: u32 = 0x09;
1350 #[doc = "- 0.75%"]
1351 pub const REG0_ADJ_10: u32 = 0x0a;
1352 #[doc = "- 1.00%"]
1353 pub const REG0_ADJ_11: u32 = 0x0b;
1354 #[doc = "- 1.25%"]
1355 pub const REG0_ADJ_12: u32 = 0x0c;
1356 #[doc = "- 1.50%"]
1357 pub const REG0_ADJ_13: u32 = 0x0d;
1358 #[doc = "- 1.75%"]
1359 pub const REG0_ADJ_14: u32 = 0x0e;
1360 #[doc = "- 2.00%"]
1361 pub const REG0_ADJ_15: u32 = 0x0f;
1362 }
1363 }
1364 #[doc = "This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation."]
1365 pub mod REG1_TARG {
1366 pub const offset: u32 = 9;
1367 pub const mask: u32 = 0x1f << offset;
1368 pub mod R {}
1369 pub mod W {}
1370 pub mod RW {
1371 #[doc = "Power gated off"]
1372 pub const REG1_TARG_0: u32 = 0;
1373 #[doc = "Target core voltage = 0.725V"]
1374 pub const REG1_TARG_1: u32 = 0x01;
1375 #[doc = "Target core voltage = 0.750V"]
1376 pub const REG1_TARG_2: u32 = 0x02;
1377 #[doc = "Target core voltage = 0.775V"]
1378 pub const REG1_TARG_3: u32 = 0x03;
1379 #[doc = "Target core voltage = 1.100V"]
1380 pub const REG1_TARG_16: u32 = 0x10;
1381 #[doc = "Target core voltage = 1.450V"]
1382 pub const REG1_TARG_30: u32 = 0x1e;
1383 #[doc = "Power FET switched full on. No regulation."]
1384 pub const REG1_TARG_31: u32 = 0x1f;
1385 }
1386 }
1387 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1388 pub mod REG1_ADJ {
1389 pub const offset: u32 = 14;
1390 pub const mask: u32 = 0x0f << offset;
1391 pub mod R {}
1392 pub mod W {}
1393 pub mod RW {
1394 #[doc = "No adjustment"]
1395 pub const REG1_ADJ_0: u32 = 0;
1396 #[doc = "+ 0.25%"]
1397 pub const REG1_ADJ_1: u32 = 0x01;
1398 #[doc = "+ 0.50%"]
1399 pub const REG1_ADJ_2: u32 = 0x02;
1400 #[doc = "+ 0.75%"]
1401 pub const REG1_ADJ_3: u32 = 0x03;
1402 #[doc = "+ 1.00%"]
1403 pub const REG1_ADJ_4: u32 = 0x04;
1404 #[doc = "+ 1.25%"]
1405 pub const REG1_ADJ_5: u32 = 0x05;
1406 #[doc = "+ 1.50%"]
1407 pub const REG1_ADJ_6: u32 = 0x06;
1408 #[doc = "+ 1.75%"]
1409 pub const REG1_ADJ_7: u32 = 0x07;
1410 #[doc = "- 0.25%"]
1411 pub const REG1_ADJ_8: u32 = 0x08;
1412 #[doc = "- 0.50%"]
1413 pub const REG1_ADJ_9: u32 = 0x09;
1414 #[doc = "- 0.75%"]
1415 pub const REG1_ADJ_10: u32 = 0x0a;
1416 #[doc = "- 1.00%"]
1417 pub const REG1_ADJ_11: u32 = 0x0b;
1418 #[doc = "- 1.25%"]
1419 pub const REG1_ADJ_12: u32 = 0x0c;
1420 #[doc = "- 1.50%"]
1421 pub const REG1_ADJ_13: u32 = 0x0d;
1422 #[doc = "- 1.75%"]
1423 pub const REG1_ADJ_14: u32 = 0x0e;
1424 #[doc = "- 2.00%"]
1425 pub const REG1_ADJ_15: u32 = 0x0f;
1426 }
1427 }
1428 #[doc = "This field defines the target voltage for the SOC power domain"]
1429 pub mod REG2_TARG {
1430 pub const offset: u32 = 18;
1431 pub const mask: u32 = 0x1f << offset;
1432 pub mod R {}
1433 pub mod W {}
1434 pub mod RW {
1435 #[doc = "Power gated off"]
1436 pub const REG2_TARG_0: u32 = 0;
1437 #[doc = "Target core voltage = 0.725V"]
1438 pub const REG2_TARG_1: u32 = 0x01;
1439 #[doc = "Target core voltage = 0.750V"]
1440 pub const REG2_TARG_2: u32 = 0x02;
1441 #[doc = "Target core voltage = 0.775V"]
1442 pub const REG2_TARG_3: u32 = 0x03;
1443 #[doc = "Target core voltage = 1.100V"]
1444 pub const REG2_TARG_16: u32 = 0x10;
1445 #[doc = "Target core voltage = 1.450V"]
1446 pub const REG2_TARG_30: u32 = 0x1e;
1447 #[doc = "Power FET switched full on. No regulation."]
1448 pub const REG2_TARG_31: u32 = 0x1f;
1449 }
1450 }
1451 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1452 pub mod REG2_ADJ {
1453 pub const offset: u32 = 23;
1454 pub const mask: u32 = 0x0f << offset;
1455 pub mod R {}
1456 pub mod W {}
1457 pub mod RW {
1458 #[doc = "No adjustment"]
1459 pub const REG2_ADJ_0: u32 = 0;
1460 #[doc = "+ 0.25%"]
1461 pub const REG2_ADJ_1: u32 = 0x01;
1462 #[doc = "+ 0.50%"]
1463 pub const REG2_ADJ_2: u32 = 0x02;
1464 #[doc = "+ 0.75%"]
1465 pub const REG2_ADJ_3: u32 = 0x03;
1466 #[doc = "+ 1.00%"]
1467 pub const REG2_ADJ_4: u32 = 0x04;
1468 #[doc = "+ 1.25%"]
1469 pub const REG2_ADJ_5: u32 = 0x05;
1470 #[doc = "+ 1.50%"]
1471 pub const REG2_ADJ_6: u32 = 0x06;
1472 #[doc = "+ 1.75%"]
1473 pub const REG2_ADJ_7: u32 = 0x07;
1474 #[doc = "- 0.25%"]
1475 pub const REG2_ADJ_8: u32 = 0x08;
1476 #[doc = "- 0.50%"]
1477 pub const REG2_ADJ_9: u32 = 0x09;
1478 #[doc = "- 0.75%"]
1479 pub const REG2_ADJ_10: u32 = 0x0a;
1480 #[doc = "- 1.00%"]
1481 pub const REG2_ADJ_11: u32 = 0x0b;
1482 #[doc = "- 1.25%"]
1483 pub const REG2_ADJ_12: u32 = 0x0c;
1484 #[doc = "- 1.50%"]
1485 pub const REG2_ADJ_13: u32 = 0x0d;
1486 #[doc = "- 1.75%"]
1487 pub const REG2_ADJ_14: u32 = 0x0e;
1488 #[doc = "- 2.00%"]
1489 pub const REG2_ADJ_15: u32 = 0x0f;
1490 }
1491 }
1492 #[doc = "Regulator voltage ramp rate."]
1493 pub mod RAMP_RATE {
1494 pub const offset: u32 = 27;
1495 pub const mask: u32 = 0x03 << offset;
1496 pub mod R {}
1497 pub mod W {}
1498 pub mod RW {
1499 #[doc = "Fast"]
1500 pub const RAMP_RATE_0: u32 = 0;
1501 #[doc = "Medium Fast"]
1502 pub const RAMP_RATE_1: u32 = 0x01;
1503 #[doc = "Medium Slow"]
1504 pub const RAMP_RATE_2: u32 = 0x02;
1505 #[doc = "Slow"]
1506 pub const RAMP_RATE_3: u32 = 0x03;
1507 }
1508 }
1509 #[doc = "If set, increases the gate drive on power gating FETs to reduce leakage in the off state"]
1510 pub mod FET_ODRIVE {
1511 pub const offset: u32 = 29;
1512 pub const mask: u32 = 0x01 << offset;
1513 pub mod R {}
1514 pub mod W {}
1515 pub mod RW {}
1516 }
1517}
1518#[doc = "Digital Regulator Core Register"]
1519pub mod REG_CORE_CLR {
1520 #[doc = "This field defines the target voltage for the ARM core power domain"]
1521 pub mod REG0_TARG {
1522 pub const offset: u32 = 0;
1523 pub const mask: u32 = 0x1f << offset;
1524 pub mod R {}
1525 pub mod W {}
1526 pub mod RW {
1527 #[doc = "Power gated off"]
1528 pub const REG0_TARG_0: u32 = 0;
1529 #[doc = "Target core voltage = 0.725V"]
1530 pub const REG0_TARG_1: u32 = 0x01;
1531 #[doc = "Target core voltage = 0.750V"]
1532 pub const REG0_TARG_2: u32 = 0x02;
1533 #[doc = "Target core voltage = 0.775V"]
1534 pub const REG0_TARG_3: u32 = 0x03;
1535 #[doc = "Target core voltage = 1.100V"]
1536 pub const REG0_TARG_16: u32 = 0x10;
1537 #[doc = "Target core voltage = 1.450V"]
1538 pub const REG0_TARG_30: u32 = 0x1e;
1539 #[doc = "Power FET switched full on. No regulation."]
1540 pub const REG0_TARG_31: u32 = 0x1f;
1541 }
1542 }
1543 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1544 pub mod REG0_ADJ {
1545 pub const offset: u32 = 5;
1546 pub const mask: u32 = 0x0f << offset;
1547 pub mod R {}
1548 pub mod W {}
1549 pub mod RW {
1550 #[doc = "No adjustment"]
1551 pub const REG0_ADJ_0: u32 = 0;
1552 #[doc = "+ 0.25%"]
1553 pub const REG0_ADJ_1: u32 = 0x01;
1554 #[doc = "+ 0.50%"]
1555 pub const REG0_ADJ_2: u32 = 0x02;
1556 #[doc = "+ 0.75%"]
1557 pub const REG0_ADJ_3: u32 = 0x03;
1558 #[doc = "+ 1.00%"]
1559 pub const REG0_ADJ_4: u32 = 0x04;
1560 #[doc = "+ 1.25%"]
1561 pub const REG0_ADJ_5: u32 = 0x05;
1562 #[doc = "+ 1.50%"]
1563 pub const REG0_ADJ_6: u32 = 0x06;
1564 #[doc = "+ 1.75%"]
1565 pub const REG0_ADJ_7: u32 = 0x07;
1566 #[doc = "- 0.25%"]
1567 pub const REG0_ADJ_8: u32 = 0x08;
1568 #[doc = "- 0.50%"]
1569 pub const REG0_ADJ_9: u32 = 0x09;
1570 #[doc = "- 0.75%"]
1571 pub const REG0_ADJ_10: u32 = 0x0a;
1572 #[doc = "- 1.00%"]
1573 pub const REG0_ADJ_11: u32 = 0x0b;
1574 #[doc = "- 1.25%"]
1575 pub const REG0_ADJ_12: u32 = 0x0c;
1576 #[doc = "- 1.50%"]
1577 pub const REG0_ADJ_13: u32 = 0x0d;
1578 #[doc = "- 1.75%"]
1579 pub const REG0_ADJ_14: u32 = 0x0e;
1580 #[doc = "- 2.00%"]
1581 pub const REG0_ADJ_15: u32 = 0x0f;
1582 }
1583 }
1584 #[doc = "This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation."]
1585 pub mod REG1_TARG {
1586 pub const offset: u32 = 9;
1587 pub const mask: u32 = 0x1f << offset;
1588 pub mod R {}
1589 pub mod W {}
1590 pub mod RW {
1591 #[doc = "Power gated off"]
1592 pub const REG1_TARG_0: u32 = 0;
1593 #[doc = "Target core voltage = 0.725V"]
1594 pub const REG1_TARG_1: u32 = 0x01;
1595 #[doc = "Target core voltage = 0.750V"]
1596 pub const REG1_TARG_2: u32 = 0x02;
1597 #[doc = "Target core voltage = 0.775V"]
1598 pub const REG1_TARG_3: u32 = 0x03;
1599 #[doc = "Target core voltage = 1.100V"]
1600 pub const REG1_TARG_16: u32 = 0x10;
1601 #[doc = "Target core voltage = 1.450V"]
1602 pub const REG1_TARG_30: u32 = 0x1e;
1603 #[doc = "Power FET switched full on. No regulation."]
1604 pub const REG1_TARG_31: u32 = 0x1f;
1605 }
1606 }
1607 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1608 pub mod REG1_ADJ {
1609 pub const offset: u32 = 14;
1610 pub const mask: u32 = 0x0f << offset;
1611 pub mod R {}
1612 pub mod W {}
1613 pub mod RW {
1614 #[doc = "No adjustment"]
1615 pub const REG1_ADJ_0: u32 = 0;
1616 #[doc = "+ 0.25%"]
1617 pub const REG1_ADJ_1: u32 = 0x01;
1618 #[doc = "+ 0.50%"]
1619 pub const REG1_ADJ_2: u32 = 0x02;
1620 #[doc = "+ 0.75%"]
1621 pub const REG1_ADJ_3: u32 = 0x03;
1622 #[doc = "+ 1.00%"]
1623 pub const REG1_ADJ_4: u32 = 0x04;
1624 #[doc = "+ 1.25%"]
1625 pub const REG1_ADJ_5: u32 = 0x05;
1626 #[doc = "+ 1.50%"]
1627 pub const REG1_ADJ_6: u32 = 0x06;
1628 #[doc = "+ 1.75%"]
1629 pub const REG1_ADJ_7: u32 = 0x07;
1630 #[doc = "- 0.25%"]
1631 pub const REG1_ADJ_8: u32 = 0x08;
1632 #[doc = "- 0.50%"]
1633 pub const REG1_ADJ_9: u32 = 0x09;
1634 #[doc = "- 0.75%"]
1635 pub const REG1_ADJ_10: u32 = 0x0a;
1636 #[doc = "- 1.00%"]
1637 pub const REG1_ADJ_11: u32 = 0x0b;
1638 #[doc = "- 1.25%"]
1639 pub const REG1_ADJ_12: u32 = 0x0c;
1640 #[doc = "- 1.50%"]
1641 pub const REG1_ADJ_13: u32 = 0x0d;
1642 #[doc = "- 1.75%"]
1643 pub const REG1_ADJ_14: u32 = 0x0e;
1644 #[doc = "- 2.00%"]
1645 pub const REG1_ADJ_15: u32 = 0x0f;
1646 }
1647 }
1648 #[doc = "This field defines the target voltage for the SOC power domain"]
1649 pub mod REG2_TARG {
1650 pub const offset: u32 = 18;
1651 pub const mask: u32 = 0x1f << offset;
1652 pub mod R {}
1653 pub mod W {}
1654 pub mod RW {
1655 #[doc = "Power gated off"]
1656 pub const REG2_TARG_0: u32 = 0;
1657 #[doc = "Target core voltage = 0.725V"]
1658 pub const REG2_TARG_1: u32 = 0x01;
1659 #[doc = "Target core voltage = 0.750V"]
1660 pub const REG2_TARG_2: u32 = 0x02;
1661 #[doc = "Target core voltage = 0.775V"]
1662 pub const REG2_TARG_3: u32 = 0x03;
1663 #[doc = "Target core voltage = 1.100V"]
1664 pub const REG2_TARG_16: u32 = 0x10;
1665 #[doc = "Target core voltage = 1.450V"]
1666 pub const REG2_TARG_30: u32 = 0x1e;
1667 #[doc = "Power FET switched full on. No regulation."]
1668 pub const REG2_TARG_31: u32 = 0x1f;
1669 }
1670 }
1671 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1672 pub mod REG2_ADJ {
1673 pub const offset: u32 = 23;
1674 pub const mask: u32 = 0x0f << offset;
1675 pub mod R {}
1676 pub mod W {}
1677 pub mod RW {
1678 #[doc = "No adjustment"]
1679 pub const REG2_ADJ_0: u32 = 0;
1680 #[doc = "+ 0.25%"]
1681 pub const REG2_ADJ_1: u32 = 0x01;
1682 #[doc = "+ 0.50%"]
1683 pub const REG2_ADJ_2: u32 = 0x02;
1684 #[doc = "+ 0.75%"]
1685 pub const REG2_ADJ_3: u32 = 0x03;
1686 #[doc = "+ 1.00%"]
1687 pub const REG2_ADJ_4: u32 = 0x04;
1688 #[doc = "+ 1.25%"]
1689 pub const REG2_ADJ_5: u32 = 0x05;
1690 #[doc = "+ 1.50%"]
1691 pub const REG2_ADJ_6: u32 = 0x06;
1692 #[doc = "+ 1.75%"]
1693 pub const REG2_ADJ_7: u32 = 0x07;
1694 #[doc = "- 0.25%"]
1695 pub const REG2_ADJ_8: u32 = 0x08;
1696 #[doc = "- 0.50%"]
1697 pub const REG2_ADJ_9: u32 = 0x09;
1698 #[doc = "- 0.75%"]
1699 pub const REG2_ADJ_10: u32 = 0x0a;
1700 #[doc = "- 1.00%"]
1701 pub const REG2_ADJ_11: u32 = 0x0b;
1702 #[doc = "- 1.25%"]
1703 pub const REG2_ADJ_12: u32 = 0x0c;
1704 #[doc = "- 1.50%"]
1705 pub const REG2_ADJ_13: u32 = 0x0d;
1706 #[doc = "- 1.75%"]
1707 pub const REG2_ADJ_14: u32 = 0x0e;
1708 #[doc = "- 2.00%"]
1709 pub const REG2_ADJ_15: u32 = 0x0f;
1710 }
1711 }
1712 #[doc = "Regulator voltage ramp rate."]
1713 pub mod RAMP_RATE {
1714 pub const offset: u32 = 27;
1715 pub const mask: u32 = 0x03 << offset;
1716 pub mod R {}
1717 pub mod W {}
1718 pub mod RW {
1719 #[doc = "Fast"]
1720 pub const RAMP_RATE_0: u32 = 0;
1721 #[doc = "Medium Fast"]
1722 pub const RAMP_RATE_1: u32 = 0x01;
1723 #[doc = "Medium Slow"]
1724 pub const RAMP_RATE_2: u32 = 0x02;
1725 #[doc = "Slow"]
1726 pub const RAMP_RATE_3: u32 = 0x03;
1727 }
1728 }
1729 #[doc = "If set, increases the gate drive on power gating FETs to reduce leakage in the off state"]
1730 pub mod FET_ODRIVE {
1731 pub const offset: u32 = 29;
1732 pub const mask: u32 = 0x01 << offset;
1733 pub mod R {}
1734 pub mod W {}
1735 pub mod RW {}
1736 }
1737}
1738#[doc = "Digital Regulator Core Register"]
1739pub mod REG_CORE_TOG {
1740 #[doc = "This field defines the target voltage for the ARM core power domain"]
1741 pub mod REG0_TARG {
1742 pub const offset: u32 = 0;
1743 pub const mask: u32 = 0x1f << offset;
1744 pub mod R {}
1745 pub mod W {}
1746 pub mod RW {
1747 #[doc = "Power gated off"]
1748 pub const REG0_TARG_0: u32 = 0;
1749 #[doc = "Target core voltage = 0.725V"]
1750 pub const REG0_TARG_1: u32 = 0x01;
1751 #[doc = "Target core voltage = 0.750V"]
1752 pub const REG0_TARG_2: u32 = 0x02;
1753 #[doc = "Target core voltage = 0.775V"]
1754 pub const REG0_TARG_3: u32 = 0x03;
1755 #[doc = "Target core voltage = 1.100V"]
1756 pub const REG0_TARG_16: u32 = 0x10;
1757 #[doc = "Target core voltage = 1.450V"]
1758 pub const REG0_TARG_30: u32 = 0x1e;
1759 #[doc = "Power FET switched full on. No regulation."]
1760 pub const REG0_TARG_31: u32 = 0x1f;
1761 }
1762 }
1763 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1764 pub mod REG0_ADJ {
1765 pub const offset: u32 = 5;
1766 pub const mask: u32 = 0x0f << offset;
1767 pub mod R {}
1768 pub mod W {}
1769 pub mod RW {
1770 #[doc = "No adjustment"]
1771 pub const REG0_ADJ_0: u32 = 0;
1772 #[doc = "+ 0.25%"]
1773 pub const REG0_ADJ_1: u32 = 0x01;
1774 #[doc = "+ 0.50%"]
1775 pub const REG0_ADJ_2: u32 = 0x02;
1776 #[doc = "+ 0.75%"]
1777 pub const REG0_ADJ_3: u32 = 0x03;
1778 #[doc = "+ 1.00%"]
1779 pub const REG0_ADJ_4: u32 = 0x04;
1780 #[doc = "+ 1.25%"]
1781 pub const REG0_ADJ_5: u32 = 0x05;
1782 #[doc = "+ 1.50%"]
1783 pub const REG0_ADJ_6: u32 = 0x06;
1784 #[doc = "+ 1.75%"]
1785 pub const REG0_ADJ_7: u32 = 0x07;
1786 #[doc = "- 0.25%"]
1787 pub const REG0_ADJ_8: u32 = 0x08;
1788 #[doc = "- 0.50%"]
1789 pub const REG0_ADJ_9: u32 = 0x09;
1790 #[doc = "- 0.75%"]
1791 pub const REG0_ADJ_10: u32 = 0x0a;
1792 #[doc = "- 1.00%"]
1793 pub const REG0_ADJ_11: u32 = 0x0b;
1794 #[doc = "- 1.25%"]
1795 pub const REG0_ADJ_12: u32 = 0x0c;
1796 #[doc = "- 1.50%"]
1797 pub const REG0_ADJ_13: u32 = 0x0d;
1798 #[doc = "- 1.75%"]
1799 pub const REG0_ADJ_14: u32 = 0x0e;
1800 #[doc = "- 2.00%"]
1801 pub const REG0_ADJ_15: u32 = 0x0f;
1802 }
1803 }
1804 #[doc = "This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation."]
1805 pub mod REG1_TARG {
1806 pub const offset: u32 = 9;
1807 pub const mask: u32 = 0x1f << offset;
1808 pub mod R {}
1809 pub mod W {}
1810 pub mod RW {
1811 #[doc = "Power gated off"]
1812 pub const REG1_TARG_0: u32 = 0;
1813 #[doc = "Target core voltage = 0.725V"]
1814 pub const REG1_TARG_1: u32 = 0x01;
1815 #[doc = "Target core voltage = 0.750V"]
1816 pub const REG1_TARG_2: u32 = 0x02;
1817 #[doc = "Target core voltage = 0.775V"]
1818 pub const REG1_TARG_3: u32 = 0x03;
1819 #[doc = "Target core voltage = 1.100V"]
1820 pub const REG1_TARG_16: u32 = 0x10;
1821 #[doc = "Target core voltage = 1.450V"]
1822 pub const REG1_TARG_30: u32 = 0x1e;
1823 #[doc = "Power FET switched full on. No regulation."]
1824 pub const REG1_TARG_31: u32 = 0x1f;
1825 }
1826 }
1827 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1828 pub mod REG1_ADJ {
1829 pub const offset: u32 = 14;
1830 pub const mask: u32 = 0x0f << offset;
1831 pub mod R {}
1832 pub mod W {}
1833 pub mod RW {
1834 #[doc = "No adjustment"]
1835 pub const REG1_ADJ_0: u32 = 0;
1836 #[doc = "+ 0.25%"]
1837 pub const REG1_ADJ_1: u32 = 0x01;
1838 #[doc = "+ 0.50%"]
1839 pub const REG1_ADJ_2: u32 = 0x02;
1840 #[doc = "+ 0.75%"]
1841 pub const REG1_ADJ_3: u32 = 0x03;
1842 #[doc = "+ 1.00%"]
1843 pub const REG1_ADJ_4: u32 = 0x04;
1844 #[doc = "+ 1.25%"]
1845 pub const REG1_ADJ_5: u32 = 0x05;
1846 #[doc = "+ 1.50%"]
1847 pub const REG1_ADJ_6: u32 = 0x06;
1848 #[doc = "+ 1.75%"]
1849 pub const REG1_ADJ_7: u32 = 0x07;
1850 #[doc = "- 0.25%"]
1851 pub const REG1_ADJ_8: u32 = 0x08;
1852 #[doc = "- 0.50%"]
1853 pub const REG1_ADJ_9: u32 = 0x09;
1854 #[doc = "- 0.75%"]
1855 pub const REG1_ADJ_10: u32 = 0x0a;
1856 #[doc = "- 1.00%"]
1857 pub const REG1_ADJ_11: u32 = 0x0b;
1858 #[doc = "- 1.25%"]
1859 pub const REG1_ADJ_12: u32 = 0x0c;
1860 #[doc = "- 1.50%"]
1861 pub const REG1_ADJ_13: u32 = 0x0d;
1862 #[doc = "- 1.75%"]
1863 pub const REG1_ADJ_14: u32 = 0x0e;
1864 #[doc = "- 2.00%"]
1865 pub const REG1_ADJ_15: u32 = 0x0f;
1866 }
1867 }
1868 #[doc = "This field defines the target voltage for the SOC power domain"]
1869 pub mod REG2_TARG {
1870 pub const offset: u32 = 18;
1871 pub const mask: u32 = 0x1f << offset;
1872 pub mod R {}
1873 pub mod W {}
1874 pub mod RW {
1875 #[doc = "Power gated off"]
1876 pub const REG2_TARG_0: u32 = 0;
1877 #[doc = "Target core voltage = 0.725V"]
1878 pub const REG2_TARG_1: u32 = 0x01;
1879 #[doc = "Target core voltage = 0.750V"]
1880 pub const REG2_TARG_2: u32 = 0x02;
1881 #[doc = "Target core voltage = 0.775V"]
1882 pub const REG2_TARG_3: u32 = 0x03;
1883 #[doc = "Target core voltage = 1.100V"]
1884 pub const REG2_TARG_16: u32 = 0x10;
1885 #[doc = "Target core voltage = 1.450V"]
1886 pub const REG2_TARG_30: u32 = 0x1e;
1887 #[doc = "Power FET switched full on. No regulation."]
1888 pub const REG2_TARG_31: u32 = 0x1f;
1889 }
1890 }
1891 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1892 pub mod REG2_ADJ {
1893 pub const offset: u32 = 23;
1894 pub const mask: u32 = 0x0f << offset;
1895 pub mod R {}
1896 pub mod W {}
1897 pub mod RW {
1898 #[doc = "No adjustment"]
1899 pub const REG2_ADJ_0: u32 = 0;
1900 #[doc = "+ 0.25%"]
1901 pub const REG2_ADJ_1: u32 = 0x01;
1902 #[doc = "+ 0.50%"]
1903 pub const REG2_ADJ_2: u32 = 0x02;
1904 #[doc = "+ 0.75%"]
1905 pub const REG2_ADJ_3: u32 = 0x03;
1906 #[doc = "+ 1.00%"]
1907 pub const REG2_ADJ_4: u32 = 0x04;
1908 #[doc = "+ 1.25%"]
1909 pub const REG2_ADJ_5: u32 = 0x05;
1910 #[doc = "+ 1.50%"]
1911 pub const REG2_ADJ_6: u32 = 0x06;
1912 #[doc = "+ 1.75%"]
1913 pub const REG2_ADJ_7: u32 = 0x07;
1914 #[doc = "- 0.25%"]
1915 pub const REG2_ADJ_8: u32 = 0x08;
1916 #[doc = "- 0.50%"]
1917 pub const REG2_ADJ_9: u32 = 0x09;
1918 #[doc = "- 0.75%"]
1919 pub const REG2_ADJ_10: u32 = 0x0a;
1920 #[doc = "- 1.00%"]
1921 pub const REG2_ADJ_11: u32 = 0x0b;
1922 #[doc = "- 1.25%"]
1923 pub const REG2_ADJ_12: u32 = 0x0c;
1924 #[doc = "- 1.50%"]
1925 pub const REG2_ADJ_13: u32 = 0x0d;
1926 #[doc = "- 1.75%"]
1927 pub const REG2_ADJ_14: u32 = 0x0e;
1928 #[doc = "- 2.00%"]
1929 pub const REG2_ADJ_15: u32 = 0x0f;
1930 }
1931 }
1932 #[doc = "Regulator voltage ramp rate."]
1933 pub mod RAMP_RATE {
1934 pub const offset: u32 = 27;
1935 pub const mask: u32 = 0x03 << offset;
1936 pub mod R {}
1937 pub mod W {}
1938 pub mod RW {
1939 #[doc = "Fast"]
1940 pub const RAMP_RATE_0: u32 = 0;
1941 #[doc = "Medium Fast"]
1942 pub const RAMP_RATE_1: u32 = 0x01;
1943 #[doc = "Medium Slow"]
1944 pub const RAMP_RATE_2: u32 = 0x02;
1945 #[doc = "Slow"]
1946 pub const RAMP_RATE_3: u32 = 0x03;
1947 }
1948 }
1949 #[doc = "If set, increases the gate drive on power gating FETs to reduce leakage in the off state"]
1950 pub mod FET_ODRIVE {
1951 pub const offset: u32 = 29;
1952 pub const mask: u32 = 0x01 << offset;
1953 pub mod R {}
1954 pub mod W {}
1955 pub mod RW {}
1956 }
1957}
1958#[doc = "Miscellaneous Register 0"]
1959pub mod MISC0 {
1960 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
1961 pub mod REFTOP_PWD {
1962 pub const offset: u32 = 0;
1963 pub const mask: u32 = 0x01 << offset;
1964 pub mod R {}
1965 pub mod W {}
1966 pub mod RW {}
1967 }
1968 #[doc = "Control bit to power down the VBG-up detection circuitry in the analog bandgap."]
1969 pub mod REFTOP_PWDVBGUP {
1970 pub const offset: u32 = 1;
1971 pub const mask: u32 = 0x01 << offset;
1972 pub mod R {}
1973 pub mod W {}
1974 pub mod RW {}
1975 }
1976 #[doc = "Control bit to enable the low-power mode in the analog bandgap."]
1977 pub mod REFTOP_LOWPOWER {
1978 pub const offset: u32 = 2;
1979 pub const mask: u32 = 0x01 << offset;
1980 pub mod R {}
1981 pub mod W {}
1982 pub mod RW {}
1983 }
1984 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
1985 pub mod REFTOP_SELFBIASOFF {
1986 pub const offset: u32 = 3;
1987 pub const mask: u32 = 0x01 << offset;
1988 pub mod R {}
1989 pub mod W {}
1990 pub mod RW {
1991 #[doc = "Uses coarse bias currents for startup"]
1992 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
1993 #[doc = "Uses bandgap-based bias currents for best performance."]
1994 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
1995 }
1996 }
1997 #[doc = "no description available"]
1998 pub mod REFTOP_VBGADJ {
1999 pub const offset: u32 = 4;
2000 pub const mask: u32 = 0x07 << offset;
2001 pub mod R {}
2002 pub mod W {}
2003 pub mod RW {
2004 #[doc = "Nominal VBG"]
2005 pub const REFTOP_VBGADJ_0: u32 = 0;
2006 #[doc = "VBG+0.78%"]
2007 pub const REFTOP_VBGADJ_1: u32 = 0x01;
2008 #[doc = "VBG+1.56%"]
2009 pub const REFTOP_VBGADJ_2: u32 = 0x02;
2010 #[doc = "VBG+2.34%"]
2011 pub const REFTOP_VBGADJ_3: u32 = 0x03;
2012 #[doc = "VBG-0.78%"]
2013 pub const REFTOP_VBGADJ_4: u32 = 0x04;
2014 #[doc = "VBG-1.56%"]
2015 pub const REFTOP_VBGADJ_5: u32 = 0x05;
2016 #[doc = "VBG-2.34%"]
2017 pub const REFTOP_VBGADJ_6: u32 = 0x06;
2018 #[doc = "VBG-3.12%"]
2019 pub const REFTOP_VBGADJ_7: u32 = 0x07;
2020 }
2021 }
2022 #[doc = "Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable."]
2023 pub mod REFTOP_VBGUP {
2024 pub const offset: u32 = 7;
2025 pub const mask: u32 = 0x01 << offset;
2026 pub mod R {}
2027 pub mod W {}
2028 pub mod RW {}
2029 }
2030 #[doc = "Configure the analog behavior in stop mode."]
2031 pub mod STOP_MODE_CONFIG {
2032 pub const offset: u32 = 10;
2033 pub const mask: u32 = 0x03 << offset;
2034 pub mod R {}
2035 pub mod W {}
2036 pub mod RW {
2037 #[doc = "SUSPEND (DSM)"]
2038 pub const STOP_MODE_CONFIG_0: u32 = 0;
2039 #[doc = "Analog regulators are ON."]
2040 pub const STANDBY: u32 = 0x01;
2041 #[doc = "STOP (lower power)"]
2042 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2043 #[doc = "STOP (very lower power)"]
2044 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2045 }
2046 }
2047 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2048 pub mod DISCON_HIGH_SNVS {
2049 pub const offset: u32 = 12;
2050 pub const mask: u32 = 0x01 << offset;
2051 pub mod R {}
2052 pub mod W {}
2053 pub mod RW {
2054 #[doc = "Turn on the switch"]
2055 pub const DISCON_HIGH_SNVS_0: u32 = 0;
2056 #[doc = "Turn off the switch"]
2057 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2058 }
2059 }
2060 #[doc = "This field determines the bias current in the 24MHz oscillator"]
2061 pub mod OSC_I {
2062 pub const offset: u32 = 13;
2063 pub const mask: u32 = 0x03 << offset;
2064 pub mod R {}
2065 pub mod W {}
2066 pub mod RW {
2067 #[doc = "Nominal"]
2068 pub const NOMINAL: u32 = 0;
2069 #[doc = "Decrease current by 12.5%"]
2070 pub const MINUS_12_5_PERCENT: u32 = 0x01;
2071 #[doc = "Decrease current by 25.0%"]
2072 pub const MINUS_25_PERCENT: u32 = 0x02;
2073 #[doc = "Decrease current by 37.5%"]
2074 pub const MINUS_37_5_PERCENT: u32 = 0x03;
2075 }
2076 }
2077 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2078 pub mod OSC_XTALOK {
2079 pub const offset: u32 = 15;
2080 pub const mask: u32 = 0x01 << offset;
2081 pub mod R {}
2082 pub mod W {}
2083 pub mod RW {}
2084 }
2085 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2086 pub mod OSC_XTALOK_EN {
2087 pub const offset: u32 = 16;
2088 pub const mask: u32 = 0x01 << offset;
2089 pub mod R {}
2090 pub mod W {}
2091 pub mod RW {}
2092 }
2093 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2094 pub mod CLKGATE_CTRL {
2095 pub const offset: u32 = 25;
2096 pub const mask: u32 = 0x01 << offset;
2097 pub mod R {}
2098 pub mod W {}
2099 pub mod RW {
2100 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2101 pub const ALLOW_AUTO_GATE: u32 = 0;
2102 #[doc = "Prevent the logic from ever gating off the clock."]
2103 pub const NO_AUTO_GATE: u32 = 0x01;
2104 }
2105 }
2106 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2107 pub mod CLKGATE_DELAY {
2108 pub const offset: u32 = 26;
2109 pub const mask: u32 = 0x07 << offset;
2110 pub mod R {}
2111 pub mod W {}
2112 pub mod RW {
2113 #[doc = "0.5ms"]
2114 pub const CLKGATE_DELAY_0: u32 = 0;
2115 #[doc = "1.0ms"]
2116 pub const CLKGATE_DELAY_1: u32 = 0x01;
2117 #[doc = "2.0ms"]
2118 pub const CLKGATE_DELAY_2: u32 = 0x02;
2119 #[doc = "3.0ms"]
2120 pub const CLKGATE_DELAY_3: u32 = 0x03;
2121 #[doc = "4.0ms"]
2122 pub const CLKGATE_DELAY_4: u32 = 0x04;
2123 #[doc = "5.0ms"]
2124 pub const CLKGATE_DELAY_5: u32 = 0x05;
2125 #[doc = "6.0ms"]
2126 pub const CLKGATE_DELAY_6: u32 = 0x06;
2127 #[doc = "7.0ms"]
2128 pub const CLKGATE_DELAY_7: u32 = 0x07;
2129 }
2130 }
2131 #[doc = "This field indicates which chip source is being used for the rtc clock."]
2132 pub mod RTC_XTAL_SOURCE {
2133 pub const offset: u32 = 29;
2134 pub const mask: u32 = 0x01 << offset;
2135 pub mod R {}
2136 pub mod W {}
2137 pub mod RW {
2138 #[doc = "Internal ring oscillator"]
2139 pub const RTC_XTAL_SOURCE_0: u32 = 0;
2140 #[doc = "RTC_XTAL"]
2141 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2142 }
2143 }
2144 #[doc = "This field powers down the 24M crystal oscillator if set true."]
2145 pub mod XTAL_24M_PWD {
2146 pub const offset: u32 = 30;
2147 pub const mask: u32 = 0x01 << offset;
2148 pub mod R {}
2149 pub mod W {}
2150 pub mod RW {}
2151 }
2152}
2153#[doc = "Miscellaneous Register 0"]
2154pub mod MISC0_SET {
2155 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2156 pub mod REFTOP_PWD {
2157 pub const offset: u32 = 0;
2158 pub const mask: u32 = 0x01 << offset;
2159 pub mod R {}
2160 pub mod W {}
2161 pub mod RW {}
2162 }
2163 #[doc = "Control bit to power down the VBG-up detection circuitry in the analog bandgap."]
2164 pub mod REFTOP_PWDVBGUP {
2165 pub const offset: u32 = 1;
2166 pub const mask: u32 = 0x01 << offset;
2167 pub mod R {}
2168 pub mod W {}
2169 pub mod RW {}
2170 }
2171 #[doc = "Control bit to enable the low-power mode in the analog bandgap."]
2172 pub mod REFTOP_LOWPOWER {
2173 pub const offset: u32 = 2;
2174 pub const mask: u32 = 0x01 << offset;
2175 pub mod R {}
2176 pub mod W {}
2177 pub mod RW {}
2178 }
2179 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2180 pub mod REFTOP_SELFBIASOFF {
2181 pub const offset: u32 = 3;
2182 pub const mask: u32 = 0x01 << offset;
2183 pub mod R {}
2184 pub mod W {}
2185 pub mod RW {
2186 #[doc = "Uses coarse bias currents for startup"]
2187 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2188 #[doc = "Uses bandgap-based bias currents for best performance."]
2189 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2190 }
2191 }
2192 #[doc = "no description available"]
2193 pub mod REFTOP_VBGADJ {
2194 pub const offset: u32 = 4;
2195 pub const mask: u32 = 0x07 << offset;
2196 pub mod R {}
2197 pub mod W {}
2198 pub mod RW {
2199 #[doc = "Nominal VBG"]
2200 pub const REFTOP_VBGADJ_0: u32 = 0;
2201 #[doc = "VBG+0.78%"]
2202 pub const REFTOP_VBGADJ_1: u32 = 0x01;
2203 #[doc = "VBG+1.56%"]
2204 pub const REFTOP_VBGADJ_2: u32 = 0x02;
2205 #[doc = "VBG+2.34%"]
2206 pub const REFTOP_VBGADJ_3: u32 = 0x03;
2207 #[doc = "VBG-0.78%"]
2208 pub const REFTOP_VBGADJ_4: u32 = 0x04;
2209 #[doc = "VBG-1.56%"]
2210 pub const REFTOP_VBGADJ_5: u32 = 0x05;
2211 #[doc = "VBG-2.34%"]
2212 pub const REFTOP_VBGADJ_6: u32 = 0x06;
2213 #[doc = "VBG-3.12%"]
2214 pub const REFTOP_VBGADJ_7: u32 = 0x07;
2215 }
2216 }
2217 #[doc = "Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable."]
2218 pub mod REFTOP_VBGUP {
2219 pub const offset: u32 = 7;
2220 pub const mask: u32 = 0x01 << offset;
2221 pub mod R {}
2222 pub mod W {}
2223 pub mod RW {}
2224 }
2225 #[doc = "Configure the analog behavior in stop mode."]
2226 pub mod STOP_MODE_CONFIG {
2227 pub const offset: u32 = 10;
2228 pub const mask: u32 = 0x03 << offset;
2229 pub mod R {}
2230 pub mod W {}
2231 pub mod RW {
2232 #[doc = "SUSPEND (DSM)"]
2233 pub const STOP_MODE_CONFIG_0: u32 = 0;
2234 #[doc = "Analog regulators are ON."]
2235 pub const STANDBY: u32 = 0x01;
2236 #[doc = "STOP (lower power)"]
2237 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2238 #[doc = "STOP (very lower power)"]
2239 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2240 }
2241 }
2242 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2243 pub mod DISCON_HIGH_SNVS {
2244 pub const offset: u32 = 12;
2245 pub const mask: u32 = 0x01 << offset;
2246 pub mod R {}
2247 pub mod W {}
2248 pub mod RW {
2249 #[doc = "Turn on the switch"]
2250 pub const DISCON_HIGH_SNVS_0: u32 = 0;
2251 #[doc = "Turn off the switch"]
2252 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2253 }
2254 }
2255 #[doc = "This field determines the bias current in the 24MHz oscillator"]
2256 pub mod OSC_I {
2257 pub const offset: u32 = 13;
2258 pub const mask: u32 = 0x03 << offset;
2259 pub mod R {}
2260 pub mod W {}
2261 pub mod RW {
2262 #[doc = "Nominal"]
2263 pub const NOMINAL: u32 = 0;
2264 #[doc = "Decrease current by 12.5%"]
2265 pub const MINUS_12_5_PERCENT: u32 = 0x01;
2266 #[doc = "Decrease current by 25.0%"]
2267 pub const MINUS_25_PERCENT: u32 = 0x02;
2268 #[doc = "Decrease current by 37.5%"]
2269 pub const MINUS_37_5_PERCENT: u32 = 0x03;
2270 }
2271 }
2272 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2273 pub mod OSC_XTALOK {
2274 pub const offset: u32 = 15;
2275 pub const mask: u32 = 0x01 << offset;
2276 pub mod R {}
2277 pub mod W {}
2278 pub mod RW {}
2279 }
2280 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2281 pub mod OSC_XTALOK_EN {
2282 pub const offset: u32 = 16;
2283 pub const mask: u32 = 0x01 << offset;
2284 pub mod R {}
2285 pub mod W {}
2286 pub mod RW {}
2287 }
2288 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2289 pub mod CLKGATE_CTRL {
2290 pub const offset: u32 = 25;
2291 pub const mask: u32 = 0x01 << offset;
2292 pub mod R {}
2293 pub mod W {}
2294 pub mod RW {
2295 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2296 pub const ALLOW_AUTO_GATE: u32 = 0;
2297 #[doc = "Prevent the logic from ever gating off the clock."]
2298 pub const NO_AUTO_GATE: u32 = 0x01;
2299 }
2300 }
2301 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2302 pub mod CLKGATE_DELAY {
2303 pub const offset: u32 = 26;
2304 pub const mask: u32 = 0x07 << offset;
2305 pub mod R {}
2306 pub mod W {}
2307 pub mod RW {
2308 #[doc = "0.5ms"]
2309 pub const CLKGATE_DELAY_0: u32 = 0;
2310 #[doc = "1.0ms"]
2311 pub const CLKGATE_DELAY_1: u32 = 0x01;
2312 #[doc = "2.0ms"]
2313 pub const CLKGATE_DELAY_2: u32 = 0x02;
2314 #[doc = "3.0ms"]
2315 pub const CLKGATE_DELAY_3: u32 = 0x03;
2316 #[doc = "4.0ms"]
2317 pub const CLKGATE_DELAY_4: u32 = 0x04;
2318 #[doc = "5.0ms"]
2319 pub const CLKGATE_DELAY_5: u32 = 0x05;
2320 #[doc = "6.0ms"]
2321 pub const CLKGATE_DELAY_6: u32 = 0x06;
2322 #[doc = "7.0ms"]
2323 pub const CLKGATE_DELAY_7: u32 = 0x07;
2324 }
2325 }
2326 #[doc = "This field indicates which chip source is being used for the rtc clock."]
2327 pub mod RTC_XTAL_SOURCE {
2328 pub const offset: u32 = 29;
2329 pub const mask: u32 = 0x01 << offset;
2330 pub mod R {}
2331 pub mod W {}
2332 pub mod RW {
2333 #[doc = "Internal ring oscillator"]
2334 pub const RTC_XTAL_SOURCE_0: u32 = 0;
2335 #[doc = "RTC_XTAL"]
2336 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2337 }
2338 }
2339 #[doc = "This field powers down the 24M crystal oscillator if set true."]
2340 pub mod XTAL_24M_PWD {
2341 pub const offset: u32 = 30;
2342 pub const mask: u32 = 0x01 << offset;
2343 pub mod R {}
2344 pub mod W {}
2345 pub mod RW {}
2346 }
2347}
2348#[doc = "Miscellaneous Register 0"]
2349pub mod MISC0_CLR {
2350 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2351 pub mod REFTOP_PWD {
2352 pub const offset: u32 = 0;
2353 pub const mask: u32 = 0x01 << offset;
2354 pub mod R {}
2355 pub mod W {}
2356 pub mod RW {}
2357 }
2358 #[doc = "Control bit to power down the VBG-up detection circuitry in the analog bandgap."]
2359 pub mod REFTOP_PWDVBGUP {
2360 pub const offset: u32 = 1;
2361 pub const mask: u32 = 0x01 << offset;
2362 pub mod R {}
2363 pub mod W {}
2364 pub mod RW {}
2365 }
2366 #[doc = "Control bit to enable the low-power mode in the analog bandgap."]
2367 pub mod REFTOP_LOWPOWER {
2368 pub const offset: u32 = 2;
2369 pub const mask: u32 = 0x01 << offset;
2370 pub mod R {}
2371 pub mod W {}
2372 pub mod RW {}
2373 }
2374 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2375 pub mod REFTOP_SELFBIASOFF {
2376 pub const offset: u32 = 3;
2377 pub const mask: u32 = 0x01 << offset;
2378 pub mod R {}
2379 pub mod W {}
2380 pub mod RW {
2381 #[doc = "Uses coarse bias currents for startup"]
2382 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2383 #[doc = "Uses bandgap-based bias currents for best performance."]
2384 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2385 }
2386 }
2387 #[doc = "no description available"]
2388 pub mod REFTOP_VBGADJ {
2389 pub const offset: u32 = 4;
2390 pub const mask: u32 = 0x07 << offset;
2391 pub mod R {}
2392 pub mod W {}
2393 pub mod RW {
2394 #[doc = "Nominal VBG"]
2395 pub const REFTOP_VBGADJ_0: u32 = 0;
2396 #[doc = "VBG+0.78%"]
2397 pub const REFTOP_VBGADJ_1: u32 = 0x01;
2398 #[doc = "VBG+1.56%"]
2399 pub const REFTOP_VBGADJ_2: u32 = 0x02;
2400 #[doc = "VBG+2.34%"]
2401 pub const REFTOP_VBGADJ_3: u32 = 0x03;
2402 #[doc = "VBG-0.78%"]
2403 pub const REFTOP_VBGADJ_4: u32 = 0x04;
2404 #[doc = "VBG-1.56%"]
2405 pub const REFTOP_VBGADJ_5: u32 = 0x05;
2406 #[doc = "VBG-2.34%"]
2407 pub const REFTOP_VBGADJ_6: u32 = 0x06;
2408 #[doc = "VBG-3.12%"]
2409 pub const REFTOP_VBGADJ_7: u32 = 0x07;
2410 }
2411 }
2412 #[doc = "Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable."]
2413 pub mod REFTOP_VBGUP {
2414 pub const offset: u32 = 7;
2415 pub const mask: u32 = 0x01 << offset;
2416 pub mod R {}
2417 pub mod W {}
2418 pub mod RW {}
2419 }
2420 #[doc = "Configure the analog behavior in stop mode."]
2421 pub mod STOP_MODE_CONFIG {
2422 pub const offset: u32 = 10;
2423 pub const mask: u32 = 0x03 << offset;
2424 pub mod R {}
2425 pub mod W {}
2426 pub mod RW {
2427 #[doc = "SUSPEND (DSM)"]
2428 pub const STOP_MODE_CONFIG_0: u32 = 0;
2429 #[doc = "Analog regulators are ON."]
2430 pub const STANDBY: u32 = 0x01;
2431 #[doc = "STOP (lower power)"]
2432 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2433 #[doc = "STOP (very lower power)"]
2434 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2435 }
2436 }
2437 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2438 pub mod DISCON_HIGH_SNVS {
2439 pub const offset: u32 = 12;
2440 pub const mask: u32 = 0x01 << offset;
2441 pub mod R {}
2442 pub mod W {}
2443 pub mod RW {
2444 #[doc = "Turn on the switch"]
2445 pub const DISCON_HIGH_SNVS_0: u32 = 0;
2446 #[doc = "Turn off the switch"]
2447 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2448 }
2449 }
2450 #[doc = "This field determines the bias current in the 24MHz oscillator"]
2451 pub mod OSC_I {
2452 pub const offset: u32 = 13;
2453 pub const mask: u32 = 0x03 << offset;
2454 pub mod R {}
2455 pub mod W {}
2456 pub mod RW {
2457 #[doc = "Nominal"]
2458 pub const NOMINAL: u32 = 0;
2459 #[doc = "Decrease current by 12.5%"]
2460 pub const MINUS_12_5_PERCENT: u32 = 0x01;
2461 #[doc = "Decrease current by 25.0%"]
2462 pub const MINUS_25_PERCENT: u32 = 0x02;
2463 #[doc = "Decrease current by 37.5%"]
2464 pub const MINUS_37_5_PERCENT: u32 = 0x03;
2465 }
2466 }
2467 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2468 pub mod OSC_XTALOK {
2469 pub const offset: u32 = 15;
2470 pub const mask: u32 = 0x01 << offset;
2471 pub mod R {}
2472 pub mod W {}
2473 pub mod RW {}
2474 }
2475 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2476 pub mod OSC_XTALOK_EN {
2477 pub const offset: u32 = 16;
2478 pub const mask: u32 = 0x01 << offset;
2479 pub mod R {}
2480 pub mod W {}
2481 pub mod RW {}
2482 }
2483 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2484 pub mod CLKGATE_CTRL {
2485 pub const offset: u32 = 25;
2486 pub const mask: u32 = 0x01 << offset;
2487 pub mod R {}
2488 pub mod W {}
2489 pub mod RW {
2490 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2491 pub const ALLOW_AUTO_GATE: u32 = 0;
2492 #[doc = "Prevent the logic from ever gating off the clock."]
2493 pub const NO_AUTO_GATE: u32 = 0x01;
2494 }
2495 }
2496 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2497 pub mod CLKGATE_DELAY {
2498 pub const offset: u32 = 26;
2499 pub const mask: u32 = 0x07 << offset;
2500 pub mod R {}
2501 pub mod W {}
2502 pub mod RW {
2503 #[doc = "0.5ms"]
2504 pub const CLKGATE_DELAY_0: u32 = 0;
2505 #[doc = "1.0ms"]
2506 pub const CLKGATE_DELAY_1: u32 = 0x01;
2507 #[doc = "2.0ms"]
2508 pub const CLKGATE_DELAY_2: u32 = 0x02;
2509 #[doc = "3.0ms"]
2510 pub const CLKGATE_DELAY_3: u32 = 0x03;
2511 #[doc = "4.0ms"]
2512 pub const CLKGATE_DELAY_4: u32 = 0x04;
2513 #[doc = "5.0ms"]
2514 pub const CLKGATE_DELAY_5: u32 = 0x05;
2515 #[doc = "6.0ms"]
2516 pub const CLKGATE_DELAY_6: u32 = 0x06;
2517 #[doc = "7.0ms"]
2518 pub const CLKGATE_DELAY_7: u32 = 0x07;
2519 }
2520 }
2521 #[doc = "This field indicates which chip source is being used for the rtc clock."]
2522 pub mod RTC_XTAL_SOURCE {
2523 pub const offset: u32 = 29;
2524 pub const mask: u32 = 0x01 << offset;
2525 pub mod R {}
2526 pub mod W {}
2527 pub mod RW {
2528 #[doc = "Internal ring oscillator"]
2529 pub const RTC_XTAL_SOURCE_0: u32 = 0;
2530 #[doc = "RTC_XTAL"]
2531 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2532 }
2533 }
2534 #[doc = "This field powers down the 24M crystal oscillator if set true."]
2535 pub mod XTAL_24M_PWD {
2536 pub const offset: u32 = 30;
2537 pub const mask: u32 = 0x01 << offset;
2538 pub mod R {}
2539 pub mod W {}
2540 pub mod RW {}
2541 }
2542}
2543#[doc = "Miscellaneous Register 0"]
2544pub mod MISC0_TOG {
2545 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2546 pub mod REFTOP_PWD {
2547 pub const offset: u32 = 0;
2548 pub const mask: u32 = 0x01 << offset;
2549 pub mod R {}
2550 pub mod W {}
2551 pub mod RW {}
2552 }
2553 #[doc = "Control bit to power down the VBG-up detection circuitry in the analog bandgap."]
2554 pub mod REFTOP_PWDVBGUP {
2555 pub const offset: u32 = 1;
2556 pub const mask: u32 = 0x01 << offset;
2557 pub mod R {}
2558 pub mod W {}
2559 pub mod RW {}
2560 }
2561 #[doc = "Control bit to enable the low-power mode in the analog bandgap."]
2562 pub mod REFTOP_LOWPOWER {
2563 pub const offset: u32 = 2;
2564 pub const mask: u32 = 0x01 << offset;
2565 pub mod R {}
2566 pub mod W {}
2567 pub mod RW {}
2568 }
2569 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2570 pub mod REFTOP_SELFBIASOFF {
2571 pub const offset: u32 = 3;
2572 pub const mask: u32 = 0x01 << offset;
2573 pub mod R {}
2574 pub mod W {}
2575 pub mod RW {
2576 #[doc = "Uses coarse bias currents for startup"]
2577 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2578 #[doc = "Uses bandgap-based bias currents for best performance."]
2579 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2580 }
2581 }
2582 #[doc = "no description available"]
2583 pub mod REFTOP_VBGADJ {
2584 pub const offset: u32 = 4;
2585 pub const mask: u32 = 0x07 << offset;
2586 pub mod R {}
2587 pub mod W {}
2588 pub mod RW {
2589 #[doc = "Nominal VBG"]
2590 pub const REFTOP_VBGADJ_0: u32 = 0;
2591 #[doc = "VBG+0.78%"]
2592 pub const REFTOP_VBGADJ_1: u32 = 0x01;
2593 #[doc = "VBG+1.56%"]
2594 pub const REFTOP_VBGADJ_2: u32 = 0x02;
2595 #[doc = "VBG+2.34%"]
2596 pub const REFTOP_VBGADJ_3: u32 = 0x03;
2597 #[doc = "VBG-0.78%"]
2598 pub const REFTOP_VBGADJ_4: u32 = 0x04;
2599 #[doc = "VBG-1.56%"]
2600 pub const REFTOP_VBGADJ_5: u32 = 0x05;
2601 #[doc = "VBG-2.34%"]
2602 pub const REFTOP_VBGADJ_6: u32 = 0x06;
2603 #[doc = "VBG-3.12%"]
2604 pub const REFTOP_VBGADJ_7: u32 = 0x07;
2605 }
2606 }
2607 #[doc = "Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable."]
2608 pub mod REFTOP_VBGUP {
2609 pub const offset: u32 = 7;
2610 pub const mask: u32 = 0x01 << offset;
2611 pub mod R {}
2612 pub mod W {}
2613 pub mod RW {}
2614 }
2615 #[doc = "Configure the analog behavior in stop mode."]
2616 pub mod STOP_MODE_CONFIG {
2617 pub const offset: u32 = 10;
2618 pub const mask: u32 = 0x03 << offset;
2619 pub mod R {}
2620 pub mod W {}
2621 pub mod RW {
2622 #[doc = "SUSPEND (DSM)"]
2623 pub const STOP_MODE_CONFIG_0: u32 = 0;
2624 #[doc = "Analog regulators are ON."]
2625 pub const STANDBY: u32 = 0x01;
2626 #[doc = "STOP (lower power)"]
2627 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2628 #[doc = "STOP (very lower power)"]
2629 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2630 }
2631 }
2632 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2633 pub mod DISCON_HIGH_SNVS {
2634 pub const offset: u32 = 12;
2635 pub const mask: u32 = 0x01 << offset;
2636 pub mod R {}
2637 pub mod W {}
2638 pub mod RW {
2639 #[doc = "Turn on the switch"]
2640 pub const DISCON_HIGH_SNVS_0: u32 = 0;
2641 #[doc = "Turn off the switch"]
2642 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2643 }
2644 }
2645 #[doc = "This field determines the bias current in the 24MHz oscillator"]
2646 pub mod OSC_I {
2647 pub const offset: u32 = 13;
2648 pub const mask: u32 = 0x03 << offset;
2649 pub mod R {}
2650 pub mod W {}
2651 pub mod RW {
2652 #[doc = "Nominal"]
2653 pub const NOMINAL: u32 = 0;
2654 #[doc = "Decrease current by 12.5%"]
2655 pub const MINUS_12_5_PERCENT: u32 = 0x01;
2656 #[doc = "Decrease current by 25.0%"]
2657 pub const MINUS_25_PERCENT: u32 = 0x02;
2658 #[doc = "Decrease current by 37.5%"]
2659 pub const MINUS_37_5_PERCENT: u32 = 0x03;
2660 }
2661 }
2662 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2663 pub mod OSC_XTALOK {
2664 pub const offset: u32 = 15;
2665 pub const mask: u32 = 0x01 << offset;
2666 pub mod R {}
2667 pub mod W {}
2668 pub mod RW {}
2669 }
2670 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2671 pub mod OSC_XTALOK_EN {
2672 pub const offset: u32 = 16;
2673 pub const mask: u32 = 0x01 << offset;
2674 pub mod R {}
2675 pub mod W {}
2676 pub mod RW {}
2677 }
2678 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2679 pub mod CLKGATE_CTRL {
2680 pub const offset: u32 = 25;
2681 pub const mask: u32 = 0x01 << offset;
2682 pub mod R {}
2683 pub mod W {}
2684 pub mod RW {
2685 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2686 pub const ALLOW_AUTO_GATE: u32 = 0;
2687 #[doc = "Prevent the logic from ever gating off the clock."]
2688 pub const NO_AUTO_GATE: u32 = 0x01;
2689 }
2690 }
2691 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2692 pub mod CLKGATE_DELAY {
2693 pub const offset: u32 = 26;
2694 pub const mask: u32 = 0x07 << offset;
2695 pub mod R {}
2696 pub mod W {}
2697 pub mod RW {
2698 #[doc = "0.5ms"]
2699 pub const CLKGATE_DELAY_0: u32 = 0;
2700 #[doc = "1.0ms"]
2701 pub const CLKGATE_DELAY_1: u32 = 0x01;
2702 #[doc = "2.0ms"]
2703 pub const CLKGATE_DELAY_2: u32 = 0x02;
2704 #[doc = "3.0ms"]
2705 pub const CLKGATE_DELAY_3: u32 = 0x03;
2706 #[doc = "4.0ms"]
2707 pub const CLKGATE_DELAY_4: u32 = 0x04;
2708 #[doc = "5.0ms"]
2709 pub const CLKGATE_DELAY_5: u32 = 0x05;
2710 #[doc = "6.0ms"]
2711 pub const CLKGATE_DELAY_6: u32 = 0x06;
2712 #[doc = "7.0ms"]
2713 pub const CLKGATE_DELAY_7: u32 = 0x07;
2714 }
2715 }
2716 #[doc = "This field indicates which chip source is being used for the rtc clock."]
2717 pub mod RTC_XTAL_SOURCE {
2718 pub const offset: u32 = 29;
2719 pub const mask: u32 = 0x01 << offset;
2720 pub mod R {}
2721 pub mod W {}
2722 pub mod RW {
2723 #[doc = "Internal ring oscillator"]
2724 pub const RTC_XTAL_SOURCE_0: u32 = 0;
2725 #[doc = "RTC_XTAL"]
2726 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2727 }
2728 }
2729 #[doc = "This field powers down the 24M crystal oscillator if set true."]
2730 pub mod XTAL_24M_PWD {
2731 pub const offset: u32 = 30;
2732 pub const mask: u32 = 0x01 << offset;
2733 pub mod R {}
2734 pub mod W {}
2735 pub mod RW {}
2736 }
2737}
2738#[doc = "Miscellaneous Register 1"]
2739pub mod MISC1 {
2740 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
2741 pub mod PFD_480_AUTOGATE_EN {
2742 pub const offset: u32 = 16;
2743 pub const mask: u32 = 0x01 << offset;
2744 pub mod R {}
2745 pub mod W {}
2746 pub mod RW {}
2747 }
2748 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
2749 pub mod PFD_528_AUTOGATE_EN {
2750 pub const offset: u32 = 17;
2751 pub const mask: u32 = 0x01 << offset;
2752 pub mod R {}
2753 pub mod W {}
2754 pub mod RW {}
2755 }
2756 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
2757 pub mod IRQ_TEMPPANIC {
2758 pub const offset: u32 = 27;
2759 pub const mask: u32 = 0x01 << offset;
2760 pub mod R {}
2761 pub mod W {}
2762 pub mod RW {}
2763 }
2764 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
2765 pub mod IRQ_TEMPLOW {
2766 pub const offset: u32 = 28;
2767 pub const mask: u32 = 0x01 << offset;
2768 pub mod R {}
2769 pub mod W {}
2770 pub mod RW {}
2771 }
2772 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
2773 pub mod IRQ_TEMPHIGH {
2774 pub const offset: u32 = 29;
2775 pub const mask: u32 = 0x01 << offset;
2776 pub mod R {}
2777 pub mod W {}
2778 pub mod RW {}
2779 }
2780 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
2781 pub mod IRQ_ANA_BO {
2782 pub const offset: u32 = 30;
2783 pub const mask: u32 = 0x01 << offset;
2784 pub mod R {}
2785 pub mod W {}
2786 pub mod RW {}
2787 }
2788 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
2789 pub mod IRQ_DIG_BO {
2790 pub const offset: u32 = 31;
2791 pub const mask: u32 = 0x01 << offset;
2792 pub mod R {}
2793 pub mod W {}
2794 pub mod RW {}
2795 }
2796}
2797#[doc = "Miscellaneous Register 1"]
2798pub mod MISC1_SET {
2799 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
2800 pub mod PFD_480_AUTOGATE_EN {
2801 pub const offset: u32 = 16;
2802 pub const mask: u32 = 0x01 << offset;
2803 pub mod R {}
2804 pub mod W {}
2805 pub mod RW {}
2806 }
2807 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
2808 pub mod PFD_528_AUTOGATE_EN {
2809 pub const offset: u32 = 17;
2810 pub const mask: u32 = 0x01 << offset;
2811 pub mod R {}
2812 pub mod W {}
2813 pub mod RW {}
2814 }
2815 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
2816 pub mod IRQ_TEMPPANIC {
2817 pub const offset: u32 = 27;
2818 pub const mask: u32 = 0x01 << offset;
2819 pub mod R {}
2820 pub mod W {}
2821 pub mod RW {}
2822 }
2823 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
2824 pub mod IRQ_TEMPLOW {
2825 pub const offset: u32 = 28;
2826 pub const mask: u32 = 0x01 << offset;
2827 pub mod R {}
2828 pub mod W {}
2829 pub mod RW {}
2830 }
2831 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
2832 pub mod IRQ_TEMPHIGH {
2833 pub const offset: u32 = 29;
2834 pub const mask: u32 = 0x01 << offset;
2835 pub mod R {}
2836 pub mod W {}
2837 pub mod RW {}
2838 }
2839 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
2840 pub mod IRQ_ANA_BO {
2841 pub const offset: u32 = 30;
2842 pub const mask: u32 = 0x01 << offset;
2843 pub mod R {}
2844 pub mod W {}
2845 pub mod RW {}
2846 }
2847 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
2848 pub mod IRQ_DIG_BO {
2849 pub const offset: u32 = 31;
2850 pub const mask: u32 = 0x01 << offset;
2851 pub mod R {}
2852 pub mod W {}
2853 pub mod RW {}
2854 }
2855}
2856#[doc = "Miscellaneous Register 1"]
2857pub mod MISC1_CLR {
2858 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
2859 pub mod PFD_480_AUTOGATE_EN {
2860 pub const offset: u32 = 16;
2861 pub const mask: u32 = 0x01 << offset;
2862 pub mod R {}
2863 pub mod W {}
2864 pub mod RW {}
2865 }
2866 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
2867 pub mod PFD_528_AUTOGATE_EN {
2868 pub const offset: u32 = 17;
2869 pub const mask: u32 = 0x01 << offset;
2870 pub mod R {}
2871 pub mod W {}
2872 pub mod RW {}
2873 }
2874 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
2875 pub mod IRQ_TEMPPANIC {
2876 pub const offset: u32 = 27;
2877 pub const mask: u32 = 0x01 << offset;
2878 pub mod R {}
2879 pub mod W {}
2880 pub mod RW {}
2881 }
2882 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
2883 pub mod IRQ_TEMPLOW {
2884 pub const offset: u32 = 28;
2885 pub const mask: u32 = 0x01 << offset;
2886 pub mod R {}
2887 pub mod W {}
2888 pub mod RW {}
2889 }
2890 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
2891 pub mod IRQ_TEMPHIGH {
2892 pub const offset: u32 = 29;
2893 pub const mask: u32 = 0x01 << offset;
2894 pub mod R {}
2895 pub mod W {}
2896 pub mod RW {}
2897 }
2898 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
2899 pub mod IRQ_ANA_BO {
2900 pub const offset: u32 = 30;
2901 pub const mask: u32 = 0x01 << offset;
2902 pub mod R {}
2903 pub mod W {}
2904 pub mod RW {}
2905 }
2906 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
2907 pub mod IRQ_DIG_BO {
2908 pub const offset: u32 = 31;
2909 pub const mask: u32 = 0x01 << offset;
2910 pub mod R {}
2911 pub mod W {}
2912 pub mod RW {}
2913 }
2914}
2915#[doc = "Miscellaneous Register 1"]
2916pub mod MISC1_TOG {
2917 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
2918 pub mod PFD_480_AUTOGATE_EN {
2919 pub const offset: u32 = 16;
2920 pub const mask: u32 = 0x01 << offset;
2921 pub mod R {}
2922 pub mod W {}
2923 pub mod RW {}
2924 }
2925 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
2926 pub mod PFD_528_AUTOGATE_EN {
2927 pub const offset: u32 = 17;
2928 pub const mask: u32 = 0x01 << offset;
2929 pub mod R {}
2930 pub mod W {}
2931 pub mod RW {}
2932 }
2933 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
2934 pub mod IRQ_TEMPPANIC {
2935 pub const offset: u32 = 27;
2936 pub const mask: u32 = 0x01 << offset;
2937 pub mod R {}
2938 pub mod W {}
2939 pub mod RW {}
2940 }
2941 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
2942 pub mod IRQ_TEMPLOW {
2943 pub const offset: u32 = 28;
2944 pub const mask: u32 = 0x01 << offset;
2945 pub mod R {}
2946 pub mod W {}
2947 pub mod RW {}
2948 }
2949 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
2950 pub mod IRQ_TEMPHIGH {
2951 pub const offset: u32 = 29;
2952 pub const mask: u32 = 0x01 << offset;
2953 pub mod R {}
2954 pub mod W {}
2955 pub mod RW {}
2956 }
2957 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
2958 pub mod IRQ_ANA_BO {
2959 pub const offset: u32 = 30;
2960 pub const mask: u32 = 0x01 << offset;
2961 pub mod R {}
2962 pub mod W {}
2963 pub mod RW {}
2964 }
2965 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
2966 pub mod IRQ_DIG_BO {
2967 pub const offset: u32 = 31;
2968 pub const mask: u32 = 0x01 << offset;
2969 pub mod R {}
2970 pub mod W {}
2971 pub mod RW {}
2972 }
2973}
2974#[doc = "Miscellaneous Control Register"]
2975pub mod MISC2 {
2976 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
2977 pub mod REG0_BO_OFFSET {
2978 pub const offset: u32 = 0;
2979 pub const mask: u32 = 0x07 << offset;
2980 pub mod R {}
2981 pub mod W {}
2982 pub mod RW {
2983 #[doc = "Brownout offset = 0.100V"]
2984 pub const REG0_BO_OFFSET_4: u32 = 0x04;
2985 #[doc = "Brownout offset = 0.175V"]
2986 pub const REG0_BO_OFFSET_7: u32 = 0x07;
2987 }
2988 }
2989 #[doc = "Reg0 brownout status bit."]
2990 pub mod REG0_BO_STATUS {
2991 pub const offset: u32 = 3;
2992 pub const mask: u32 = 0x01 << offset;
2993 pub mod R {}
2994 pub mod W {}
2995 pub mod RW {
2996 #[doc = "Brownout, supply is below target minus brownout offset."]
2997 pub const REG0_BO_STATUS_1: u32 = 0x01;
2998 }
2999 }
3000 #[doc = "Enables the brownout detection."]
3001 pub mod REG0_ENABLE_BO {
3002 pub const offset: u32 = 5;
3003 pub const mask: u32 = 0x01 << offset;
3004 pub mod R {}
3005 pub mod W {}
3006 pub mod RW {}
3007 }
3008 #[doc = "Default value of \"0\""]
3009 pub mod PLL3_DISABLE {
3010 pub const offset: u32 = 7;
3011 pub const mask: u32 = 0x01 << offset;
3012 pub mod R {}
3013 pub mod W {}
3014 pub mod RW {}
3015 }
3016 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3017 pub mod REG1_BO_OFFSET {
3018 pub const offset: u32 = 8;
3019 pub const mask: u32 = 0x07 << offset;
3020 pub mod R {}
3021 pub mod W {}
3022 pub mod RW {
3023 #[doc = "Brownout offset = 0.100V"]
3024 pub const REG1_BO_OFFSET_4: u32 = 0x04;
3025 #[doc = "Brownout offset = 0.175V"]
3026 pub const REG1_BO_OFFSET_7: u32 = 0x07;
3027 }
3028 }
3029 #[doc = "Reg1 brownout status bit."]
3030 pub mod REG1_BO_STATUS {
3031 pub const offset: u32 = 11;
3032 pub const mask: u32 = 0x01 << offset;
3033 pub mod R {}
3034 pub mod W {}
3035 pub mod RW {
3036 #[doc = "Brownout, supply is below target minus brownout offset."]
3037 pub const REG1_BO_STATUS_1: u32 = 0x01;
3038 }
3039 }
3040 #[doc = "Enables the brownout detection."]
3041 pub mod REG1_ENABLE_BO {
3042 pub const offset: u32 = 13;
3043 pub const mask: u32 = 0x01 << offset;
3044 pub mod R {}
3045 pub mod W {}
3046 pub mod RW {}
3047 }
3048 #[doc = "LSB of Post-divider for Audio PLL"]
3049 pub mod AUDIO_DIV_LSB {
3050 pub const offset: u32 = 15;
3051 pub const mask: u32 = 0x01 << offset;
3052 pub mod R {}
3053 pub mod W {}
3054 pub mod RW {
3055 #[doc = "divide by 1 (Default)"]
3056 pub const AUDIO_DIV_LSB_0: u32 = 0;
3057 #[doc = "divide by 2"]
3058 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3059 }
3060 }
3061 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3062 pub mod REG2_BO_OFFSET {
3063 pub const offset: u32 = 16;
3064 pub const mask: u32 = 0x07 << offset;
3065 pub mod R {}
3066 pub mod W {}
3067 pub mod RW {
3068 #[doc = "Brownout offset = 0.100V"]
3069 pub const REG2_BO_OFFSET_4: u32 = 0x04;
3070 #[doc = "Brownout offset = 0.175V"]
3071 pub const REG2_BO_OFFSET_7: u32 = 0x07;
3072 }
3073 }
3074 #[doc = "Reg2 brownout status bit."]
3075 pub mod REG2_BO_STATUS {
3076 pub const offset: u32 = 19;
3077 pub const mask: u32 = 0x01 << offset;
3078 pub mod R {}
3079 pub mod W {}
3080 pub mod RW {}
3081 }
3082 #[doc = "Enables the brownout detection."]
3083 pub mod REG2_ENABLE_BO {
3084 pub const offset: u32 = 21;
3085 pub const mask: u32 = 0x01 << offset;
3086 pub mod R {}
3087 pub mod W {}
3088 pub mod RW {}
3089 }
3090 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3091 pub mod REG2_OK {
3092 pub const offset: u32 = 22;
3093 pub const mask: u32 = 0x01 << offset;
3094 pub mod R {}
3095 pub mod W {}
3096 pub mod RW {}
3097 }
3098 #[doc = "MSB of Post-divider for Audio PLL"]
3099 pub mod AUDIO_DIV_MSB {
3100 pub const offset: u32 = 23;
3101 pub const mask: u32 = 0x01 << offset;
3102 pub mod R {}
3103 pub mod W {}
3104 pub mod RW {
3105 #[doc = "divide by 1 (Default)"]
3106 pub const AUDIO_DIV_MSB_0: u32 = 0;
3107 #[doc = "divide by 2"]
3108 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3109 }
3110 }
3111 #[doc = "Number of clock periods (24MHz clock)."]
3112 pub mod REG0_STEP_TIME {
3113 pub const offset: u32 = 24;
3114 pub const mask: u32 = 0x03 << offset;
3115 pub mod R {}
3116 pub mod W {}
3117 pub mod RW {
3118 #[doc = "64"]
3119 pub const _64_CLOCKS: u32 = 0;
3120 #[doc = "128"]
3121 pub const _128_CLOCKS: u32 = 0x01;
3122 #[doc = "256"]
3123 pub const _256_CLOCKS: u32 = 0x02;
3124 #[doc = "512"]
3125 pub const _512_CLOCKS: u32 = 0x03;
3126 }
3127 }
3128 #[doc = "Number of clock periods (24MHz clock)."]
3129 pub mod REG1_STEP_TIME {
3130 pub const offset: u32 = 26;
3131 pub const mask: u32 = 0x03 << offset;
3132 pub mod R {}
3133 pub mod W {}
3134 pub mod RW {
3135 #[doc = "64"]
3136 pub const _64_CLOCKS: u32 = 0;
3137 #[doc = "128"]
3138 pub const _128_CLOCKS: u32 = 0x01;
3139 #[doc = "256"]
3140 pub const _256_CLOCKS: u32 = 0x02;
3141 #[doc = "512"]
3142 pub const _512_CLOCKS: u32 = 0x03;
3143 }
3144 }
3145 #[doc = "Number of clock periods (24MHz clock)."]
3146 pub mod REG2_STEP_TIME {
3147 pub const offset: u32 = 28;
3148 pub const mask: u32 = 0x03 << offset;
3149 pub mod R {}
3150 pub mod W {}
3151 pub mod RW {
3152 #[doc = "64"]
3153 pub const _64_CLOCKS: u32 = 0;
3154 #[doc = "128"]
3155 pub const _128_CLOCKS: u32 = 0x01;
3156 #[doc = "256"]
3157 pub const _256_CLOCKS: u32 = 0x02;
3158 #[doc = "512"]
3159 pub const _512_CLOCKS: u32 = 0x03;
3160 }
3161 }
3162}
3163#[doc = "Miscellaneous Control Register"]
3164pub mod MISC2_SET {
3165 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
3166 pub mod REG0_BO_OFFSET {
3167 pub const offset: u32 = 0;
3168 pub const mask: u32 = 0x07 << offset;
3169 pub mod R {}
3170 pub mod W {}
3171 pub mod RW {
3172 #[doc = "Brownout offset = 0.100V"]
3173 pub const REG0_BO_OFFSET_4: u32 = 0x04;
3174 #[doc = "Brownout offset = 0.175V"]
3175 pub const REG0_BO_OFFSET_7: u32 = 0x07;
3176 }
3177 }
3178 #[doc = "Reg0 brownout status bit."]
3179 pub mod REG0_BO_STATUS {
3180 pub const offset: u32 = 3;
3181 pub const mask: u32 = 0x01 << offset;
3182 pub mod R {}
3183 pub mod W {}
3184 pub mod RW {
3185 #[doc = "Brownout, supply is below target minus brownout offset."]
3186 pub const REG0_BO_STATUS_1: u32 = 0x01;
3187 }
3188 }
3189 #[doc = "Enables the brownout detection."]
3190 pub mod REG0_ENABLE_BO {
3191 pub const offset: u32 = 5;
3192 pub const mask: u32 = 0x01 << offset;
3193 pub mod R {}
3194 pub mod W {}
3195 pub mod RW {}
3196 }
3197 #[doc = "Default value of \"0\""]
3198 pub mod PLL3_DISABLE {
3199 pub const offset: u32 = 7;
3200 pub const mask: u32 = 0x01 << offset;
3201 pub mod R {}
3202 pub mod W {}
3203 pub mod RW {}
3204 }
3205 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3206 pub mod REG1_BO_OFFSET {
3207 pub const offset: u32 = 8;
3208 pub const mask: u32 = 0x07 << offset;
3209 pub mod R {}
3210 pub mod W {}
3211 pub mod RW {
3212 #[doc = "Brownout offset = 0.100V"]
3213 pub const REG1_BO_OFFSET_4: u32 = 0x04;
3214 #[doc = "Brownout offset = 0.175V"]
3215 pub const REG1_BO_OFFSET_7: u32 = 0x07;
3216 }
3217 }
3218 #[doc = "Reg1 brownout status bit."]
3219 pub mod REG1_BO_STATUS {
3220 pub const offset: u32 = 11;
3221 pub const mask: u32 = 0x01 << offset;
3222 pub mod R {}
3223 pub mod W {}
3224 pub mod RW {
3225 #[doc = "Brownout, supply is below target minus brownout offset."]
3226 pub const REG1_BO_STATUS_1: u32 = 0x01;
3227 }
3228 }
3229 #[doc = "Enables the brownout detection."]
3230 pub mod REG1_ENABLE_BO {
3231 pub const offset: u32 = 13;
3232 pub const mask: u32 = 0x01 << offset;
3233 pub mod R {}
3234 pub mod W {}
3235 pub mod RW {}
3236 }
3237 #[doc = "LSB of Post-divider for Audio PLL"]
3238 pub mod AUDIO_DIV_LSB {
3239 pub const offset: u32 = 15;
3240 pub const mask: u32 = 0x01 << offset;
3241 pub mod R {}
3242 pub mod W {}
3243 pub mod RW {
3244 #[doc = "divide by 1 (Default)"]
3245 pub const AUDIO_DIV_LSB_0: u32 = 0;
3246 #[doc = "divide by 2"]
3247 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3248 }
3249 }
3250 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3251 pub mod REG2_BO_OFFSET {
3252 pub const offset: u32 = 16;
3253 pub const mask: u32 = 0x07 << offset;
3254 pub mod R {}
3255 pub mod W {}
3256 pub mod RW {
3257 #[doc = "Brownout offset = 0.100V"]
3258 pub const REG2_BO_OFFSET_4: u32 = 0x04;
3259 #[doc = "Brownout offset = 0.175V"]
3260 pub const REG2_BO_OFFSET_7: u32 = 0x07;
3261 }
3262 }
3263 #[doc = "Reg2 brownout status bit."]
3264 pub mod REG2_BO_STATUS {
3265 pub const offset: u32 = 19;
3266 pub const mask: u32 = 0x01 << offset;
3267 pub mod R {}
3268 pub mod W {}
3269 pub mod RW {}
3270 }
3271 #[doc = "Enables the brownout detection."]
3272 pub mod REG2_ENABLE_BO {
3273 pub const offset: u32 = 21;
3274 pub const mask: u32 = 0x01 << offset;
3275 pub mod R {}
3276 pub mod W {}
3277 pub mod RW {}
3278 }
3279 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3280 pub mod REG2_OK {
3281 pub const offset: u32 = 22;
3282 pub const mask: u32 = 0x01 << offset;
3283 pub mod R {}
3284 pub mod W {}
3285 pub mod RW {}
3286 }
3287 #[doc = "MSB of Post-divider for Audio PLL"]
3288 pub mod AUDIO_DIV_MSB {
3289 pub const offset: u32 = 23;
3290 pub const mask: u32 = 0x01 << offset;
3291 pub mod R {}
3292 pub mod W {}
3293 pub mod RW {
3294 #[doc = "divide by 1 (Default)"]
3295 pub const AUDIO_DIV_MSB_0: u32 = 0;
3296 #[doc = "divide by 2"]
3297 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3298 }
3299 }
3300 #[doc = "Number of clock periods (24MHz clock)."]
3301 pub mod REG0_STEP_TIME {
3302 pub const offset: u32 = 24;
3303 pub const mask: u32 = 0x03 << offset;
3304 pub mod R {}
3305 pub mod W {}
3306 pub mod RW {
3307 #[doc = "64"]
3308 pub const _64_CLOCKS: u32 = 0;
3309 #[doc = "128"]
3310 pub const _128_CLOCKS: u32 = 0x01;
3311 #[doc = "256"]
3312 pub const _256_CLOCKS: u32 = 0x02;
3313 #[doc = "512"]
3314 pub const _512_CLOCKS: u32 = 0x03;
3315 }
3316 }
3317 #[doc = "Number of clock periods (24MHz clock)."]
3318 pub mod REG1_STEP_TIME {
3319 pub const offset: u32 = 26;
3320 pub const mask: u32 = 0x03 << offset;
3321 pub mod R {}
3322 pub mod W {}
3323 pub mod RW {
3324 #[doc = "64"]
3325 pub const _64_CLOCKS: u32 = 0;
3326 #[doc = "128"]
3327 pub const _128_CLOCKS: u32 = 0x01;
3328 #[doc = "256"]
3329 pub const _256_CLOCKS: u32 = 0x02;
3330 #[doc = "512"]
3331 pub const _512_CLOCKS: u32 = 0x03;
3332 }
3333 }
3334 #[doc = "Number of clock periods (24MHz clock)."]
3335 pub mod REG2_STEP_TIME {
3336 pub const offset: u32 = 28;
3337 pub const mask: u32 = 0x03 << offset;
3338 pub mod R {}
3339 pub mod W {}
3340 pub mod RW {
3341 #[doc = "64"]
3342 pub const _64_CLOCKS: u32 = 0;
3343 #[doc = "128"]
3344 pub const _128_CLOCKS: u32 = 0x01;
3345 #[doc = "256"]
3346 pub const _256_CLOCKS: u32 = 0x02;
3347 #[doc = "512"]
3348 pub const _512_CLOCKS: u32 = 0x03;
3349 }
3350 }
3351}
3352#[doc = "Miscellaneous Control Register"]
3353pub mod MISC2_CLR {
3354 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
3355 pub mod REG0_BO_OFFSET {
3356 pub const offset: u32 = 0;
3357 pub const mask: u32 = 0x07 << offset;
3358 pub mod R {}
3359 pub mod W {}
3360 pub mod RW {
3361 #[doc = "Brownout offset = 0.100V"]
3362 pub const REG0_BO_OFFSET_4: u32 = 0x04;
3363 #[doc = "Brownout offset = 0.175V"]
3364 pub const REG0_BO_OFFSET_7: u32 = 0x07;
3365 }
3366 }
3367 #[doc = "Reg0 brownout status bit."]
3368 pub mod REG0_BO_STATUS {
3369 pub const offset: u32 = 3;
3370 pub const mask: u32 = 0x01 << offset;
3371 pub mod R {}
3372 pub mod W {}
3373 pub mod RW {
3374 #[doc = "Brownout, supply is below target minus brownout offset."]
3375 pub const REG0_BO_STATUS_1: u32 = 0x01;
3376 }
3377 }
3378 #[doc = "Enables the brownout detection."]
3379 pub mod REG0_ENABLE_BO {
3380 pub const offset: u32 = 5;
3381 pub const mask: u32 = 0x01 << offset;
3382 pub mod R {}
3383 pub mod W {}
3384 pub mod RW {}
3385 }
3386 #[doc = "Default value of \"0\""]
3387 pub mod PLL3_DISABLE {
3388 pub const offset: u32 = 7;
3389 pub const mask: u32 = 0x01 << offset;
3390 pub mod R {}
3391 pub mod W {}
3392 pub mod RW {}
3393 }
3394 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3395 pub mod REG1_BO_OFFSET {
3396 pub const offset: u32 = 8;
3397 pub const mask: u32 = 0x07 << offset;
3398 pub mod R {}
3399 pub mod W {}
3400 pub mod RW {
3401 #[doc = "Brownout offset = 0.100V"]
3402 pub const REG1_BO_OFFSET_4: u32 = 0x04;
3403 #[doc = "Brownout offset = 0.175V"]
3404 pub const REG1_BO_OFFSET_7: u32 = 0x07;
3405 }
3406 }
3407 #[doc = "Reg1 brownout status bit."]
3408 pub mod REG1_BO_STATUS {
3409 pub const offset: u32 = 11;
3410 pub const mask: u32 = 0x01 << offset;
3411 pub mod R {}
3412 pub mod W {}
3413 pub mod RW {
3414 #[doc = "Brownout, supply is below target minus brownout offset."]
3415 pub const REG1_BO_STATUS_1: u32 = 0x01;
3416 }
3417 }
3418 #[doc = "Enables the brownout detection."]
3419 pub mod REG1_ENABLE_BO {
3420 pub const offset: u32 = 13;
3421 pub const mask: u32 = 0x01 << offset;
3422 pub mod R {}
3423 pub mod W {}
3424 pub mod RW {}
3425 }
3426 #[doc = "LSB of Post-divider for Audio PLL"]
3427 pub mod AUDIO_DIV_LSB {
3428 pub const offset: u32 = 15;
3429 pub const mask: u32 = 0x01 << offset;
3430 pub mod R {}
3431 pub mod W {}
3432 pub mod RW {
3433 #[doc = "divide by 1 (Default)"]
3434 pub const AUDIO_DIV_LSB_0: u32 = 0;
3435 #[doc = "divide by 2"]
3436 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3437 }
3438 }
3439 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3440 pub mod REG2_BO_OFFSET {
3441 pub const offset: u32 = 16;
3442 pub const mask: u32 = 0x07 << offset;
3443 pub mod R {}
3444 pub mod W {}
3445 pub mod RW {
3446 #[doc = "Brownout offset = 0.100V"]
3447 pub const REG2_BO_OFFSET_4: u32 = 0x04;
3448 #[doc = "Brownout offset = 0.175V"]
3449 pub const REG2_BO_OFFSET_7: u32 = 0x07;
3450 }
3451 }
3452 #[doc = "Reg2 brownout status bit."]
3453 pub mod REG2_BO_STATUS {
3454 pub const offset: u32 = 19;
3455 pub const mask: u32 = 0x01 << offset;
3456 pub mod R {}
3457 pub mod W {}
3458 pub mod RW {}
3459 }
3460 #[doc = "Enables the brownout detection."]
3461 pub mod REG2_ENABLE_BO {
3462 pub const offset: u32 = 21;
3463 pub const mask: u32 = 0x01 << offset;
3464 pub mod R {}
3465 pub mod W {}
3466 pub mod RW {}
3467 }
3468 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3469 pub mod REG2_OK {
3470 pub const offset: u32 = 22;
3471 pub const mask: u32 = 0x01 << offset;
3472 pub mod R {}
3473 pub mod W {}
3474 pub mod RW {}
3475 }
3476 #[doc = "MSB of Post-divider for Audio PLL"]
3477 pub mod AUDIO_DIV_MSB {
3478 pub const offset: u32 = 23;
3479 pub const mask: u32 = 0x01 << offset;
3480 pub mod R {}
3481 pub mod W {}
3482 pub mod RW {
3483 #[doc = "divide by 1 (Default)"]
3484 pub const AUDIO_DIV_MSB_0: u32 = 0;
3485 #[doc = "divide by 2"]
3486 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3487 }
3488 }
3489 #[doc = "Number of clock periods (24MHz clock)."]
3490 pub mod REG0_STEP_TIME {
3491 pub const offset: u32 = 24;
3492 pub const mask: u32 = 0x03 << offset;
3493 pub mod R {}
3494 pub mod W {}
3495 pub mod RW {
3496 #[doc = "64"]
3497 pub const _64_CLOCKS: u32 = 0;
3498 #[doc = "128"]
3499 pub const _128_CLOCKS: u32 = 0x01;
3500 #[doc = "256"]
3501 pub const _256_CLOCKS: u32 = 0x02;
3502 #[doc = "512"]
3503 pub const _512_CLOCKS: u32 = 0x03;
3504 }
3505 }
3506 #[doc = "Number of clock periods (24MHz clock)."]
3507 pub mod REG1_STEP_TIME {
3508 pub const offset: u32 = 26;
3509 pub const mask: u32 = 0x03 << offset;
3510 pub mod R {}
3511 pub mod W {}
3512 pub mod RW {
3513 #[doc = "64"]
3514 pub const _64_CLOCKS: u32 = 0;
3515 #[doc = "128"]
3516 pub const _128_CLOCKS: u32 = 0x01;
3517 #[doc = "256"]
3518 pub const _256_CLOCKS: u32 = 0x02;
3519 #[doc = "512"]
3520 pub const _512_CLOCKS: u32 = 0x03;
3521 }
3522 }
3523 #[doc = "Number of clock periods (24MHz clock)."]
3524 pub mod REG2_STEP_TIME {
3525 pub const offset: u32 = 28;
3526 pub const mask: u32 = 0x03 << offset;
3527 pub mod R {}
3528 pub mod W {}
3529 pub mod RW {
3530 #[doc = "64"]
3531 pub const _64_CLOCKS: u32 = 0;
3532 #[doc = "128"]
3533 pub const _128_CLOCKS: u32 = 0x01;
3534 #[doc = "256"]
3535 pub const _256_CLOCKS: u32 = 0x02;
3536 #[doc = "512"]
3537 pub const _512_CLOCKS: u32 = 0x03;
3538 }
3539 }
3540}
3541#[doc = "Miscellaneous Control Register"]
3542pub mod MISC2_TOG {
3543 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
3544 pub mod REG0_BO_OFFSET {
3545 pub const offset: u32 = 0;
3546 pub const mask: u32 = 0x07 << offset;
3547 pub mod R {}
3548 pub mod W {}
3549 pub mod RW {
3550 #[doc = "Brownout offset = 0.100V"]
3551 pub const REG0_BO_OFFSET_4: u32 = 0x04;
3552 #[doc = "Brownout offset = 0.175V"]
3553 pub const REG0_BO_OFFSET_7: u32 = 0x07;
3554 }
3555 }
3556 #[doc = "Reg0 brownout status bit."]
3557 pub mod REG0_BO_STATUS {
3558 pub const offset: u32 = 3;
3559 pub const mask: u32 = 0x01 << offset;
3560 pub mod R {}
3561 pub mod W {}
3562 pub mod RW {
3563 #[doc = "Brownout, supply is below target minus brownout offset."]
3564 pub const REG0_BO_STATUS_1: u32 = 0x01;
3565 }
3566 }
3567 #[doc = "Enables the brownout detection."]
3568 pub mod REG0_ENABLE_BO {
3569 pub const offset: u32 = 5;
3570 pub const mask: u32 = 0x01 << offset;
3571 pub mod R {}
3572 pub mod W {}
3573 pub mod RW {}
3574 }
3575 #[doc = "Default value of \"0\""]
3576 pub mod PLL3_DISABLE {
3577 pub const offset: u32 = 7;
3578 pub const mask: u32 = 0x01 << offset;
3579 pub mod R {}
3580 pub mod W {}
3581 pub mod RW {}
3582 }
3583 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3584 pub mod REG1_BO_OFFSET {
3585 pub const offset: u32 = 8;
3586 pub const mask: u32 = 0x07 << offset;
3587 pub mod R {}
3588 pub mod W {}
3589 pub mod RW {
3590 #[doc = "Brownout offset = 0.100V"]
3591 pub const REG1_BO_OFFSET_4: u32 = 0x04;
3592 #[doc = "Brownout offset = 0.175V"]
3593 pub const REG1_BO_OFFSET_7: u32 = 0x07;
3594 }
3595 }
3596 #[doc = "Reg1 brownout status bit."]
3597 pub mod REG1_BO_STATUS {
3598 pub const offset: u32 = 11;
3599 pub const mask: u32 = 0x01 << offset;
3600 pub mod R {}
3601 pub mod W {}
3602 pub mod RW {
3603 #[doc = "Brownout, supply is below target minus brownout offset."]
3604 pub const REG1_BO_STATUS_1: u32 = 0x01;
3605 }
3606 }
3607 #[doc = "Enables the brownout detection."]
3608 pub mod REG1_ENABLE_BO {
3609 pub const offset: u32 = 13;
3610 pub const mask: u32 = 0x01 << offset;
3611 pub mod R {}
3612 pub mod W {}
3613 pub mod RW {}
3614 }
3615 #[doc = "LSB of Post-divider for Audio PLL"]
3616 pub mod AUDIO_DIV_LSB {
3617 pub const offset: u32 = 15;
3618 pub const mask: u32 = 0x01 << offset;
3619 pub mod R {}
3620 pub mod W {}
3621 pub mod RW {
3622 #[doc = "divide by 1 (Default)"]
3623 pub const AUDIO_DIV_LSB_0: u32 = 0;
3624 #[doc = "divide by 2"]
3625 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3626 }
3627 }
3628 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3629 pub mod REG2_BO_OFFSET {
3630 pub const offset: u32 = 16;
3631 pub const mask: u32 = 0x07 << offset;
3632 pub mod R {}
3633 pub mod W {}
3634 pub mod RW {
3635 #[doc = "Brownout offset = 0.100V"]
3636 pub const REG2_BO_OFFSET_4: u32 = 0x04;
3637 #[doc = "Brownout offset = 0.175V"]
3638 pub const REG2_BO_OFFSET_7: u32 = 0x07;
3639 }
3640 }
3641 #[doc = "Reg2 brownout status bit."]
3642 pub mod REG2_BO_STATUS {
3643 pub const offset: u32 = 19;
3644 pub const mask: u32 = 0x01 << offset;
3645 pub mod R {}
3646 pub mod W {}
3647 pub mod RW {}
3648 }
3649 #[doc = "Enables the brownout detection."]
3650 pub mod REG2_ENABLE_BO {
3651 pub const offset: u32 = 21;
3652 pub const mask: u32 = 0x01 << offset;
3653 pub mod R {}
3654 pub mod W {}
3655 pub mod RW {}
3656 }
3657 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3658 pub mod REG2_OK {
3659 pub const offset: u32 = 22;
3660 pub const mask: u32 = 0x01 << offset;
3661 pub mod R {}
3662 pub mod W {}
3663 pub mod RW {}
3664 }
3665 #[doc = "MSB of Post-divider for Audio PLL"]
3666 pub mod AUDIO_DIV_MSB {
3667 pub const offset: u32 = 23;
3668 pub const mask: u32 = 0x01 << offset;
3669 pub mod R {}
3670 pub mod W {}
3671 pub mod RW {
3672 #[doc = "divide by 1 (Default)"]
3673 pub const AUDIO_DIV_MSB_0: u32 = 0;
3674 #[doc = "divide by 2"]
3675 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3676 }
3677 }
3678 #[doc = "Number of clock periods (24MHz clock)."]
3679 pub mod REG0_STEP_TIME {
3680 pub const offset: u32 = 24;
3681 pub const mask: u32 = 0x03 << offset;
3682 pub mod R {}
3683 pub mod W {}
3684 pub mod RW {
3685 #[doc = "64"]
3686 pub const _64_CLOCKS: u32 = 0;
3687 #[doc = "128"]
3688 pub const _128_CLOCKS: u32 = 0x01;
3689 #[doc = "256"]
3690 pub const _256_CLOCKS: u32 = 0x02;
3691 #[doc = "512"]
3692 pub const _512_CLOCKS: u32 = 0x03;
3693 }
3694 }
3695 #[doc = "Number of clock periods (24MHz clock)."]
3696 pub mod REG1_STEP_TIME {
3697 pub const offset: u32 = 26;
3698 pub const mask: u32 = 0x03 << offset;
3699 pub mod R {}
3700 pub mod W {}
3701 pub mod RW {
3702 #[doc = "64"]
3703 pub const _64_CLOCKS: u32 = 0;
3704 #[doc = "128"]
3705 pub const _128_CLOCKS: u32 = 0x01;
3706 #[doc = "256"]
3707 pub const _256_CLOCKS: u32 = 0x02;
3708 #[doc = "512"]
3709 pub const _512_CLOCKS: u32 = 0x03;
3710 }
3711 }
3712 #[doc = "Number of clock periods (24MHz clock)."]
3713 pub mod REG2_STEP_TIME {
3714 pub const offset: u32 = 28;
3715 pub const mask: u32 = 0x03 << offset;
3716 pub mod R {}
3717 pub mod W {}
3718 pub mod RW {
3719 #[doc = "64"]
3720 pub const _64_CLOCKS: u32 = 0;
3721 #[doc = "128"]
3722 pub const _128_CLOCKS: u32 = 0x01;
3723 #[doc = "256"]
3724 pub const _256_CLOCKS: u32 = 0x02;
3725 #[doc = "512"]
3726 pub const _512_CLOCKS: u32 = 0x03;
3727 }
3728 }
3729}