nrf52840_pac/pdm/
pdmclkctrl.rs

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1#[doc = "Register `PDMCLKCTRL` reader"]
2pub struct R(crate::R<PDMCLKCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PDMCLKCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PDMCLKCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PDMCLKCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PDMCLKCTRL` writer"]
17pub struct W(crate::W<PDMCLKCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PDMCLKCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PDMCLKCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PDMCLKCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `FREQ` reader - PDM_CLK frequency"]
38pub type FREQ_R = crate::FieldReader<u32, FREQ_A>;
39#[doc = "PDM_CLK frequency\n\nValue on reset: 138412032"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41#[repr(u32)]
42pub enum FREQ_A {
43    #[doc = "134217728: PDM_CLK = 32 MHz / 32 = 1.000 MHz"]
44    _1000K = 134217728,
45    #[doc = "138412032: PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64."]
46    DEFAULT = 138412032,
47    #[doc = "142606336: PDM_CLK = 32 MHz / 30 = 1.067 MHz"]
48    _1067K = 142606336,
49    #[doc = "159383552: PDM_CLK = 32 MHz / 26 = 1.231 MHz"]
50    _1231K = 159383552,
51    #[doc = "167772160: PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80."]
52    _1280K = 167772160,
53    #[doc = "176160768: PDM_CLK = 32 MHz / 24 = 1.333 MHz"]
54    _1333K = 176160768,
55}
56impl From<FREQ_A> for u32 {
57    #[inline(always)]
58    fn from(variant: FREQ_A) -> Self {
59        variant as _
60    }
61}
62impl FREQ_R {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> Option<FREQ_A> {
66        match self.bits {
67            134217728 => Some(FREQ_A::_1000K),
68            138412032 => Some(FREQ_A::DEFAULT),
69            142606336 => Some(FREQ_A::_1067K),
70            159383552 => Some(FREQ_A::_1231K),
71            167772160 => Some(FREQ_A::_1280K),
72            176160768 => Some(FREQ_A::_1333K),
73            _ => None,
74        }
75    }
76    #[doc = "Checks if the value of the field is `_1000K`"]
77    #[inline(always)]
78    pub fn is_1000k(&self) -> bool {
79        *self == FREQ_A::_1000K
80    }
81    #[doc = "Checks if the value of the field is `DEFAULT`"]
82    #[inline(always)]
83    pub fn is_default(&self) -> bool {
84        *self == FREQ_A::DEFAULT
85    }
86    #[doc = "Checks if the value of the field is `_1067K`"]
87    #[inline(always)]
88    pub fn is_1067k(&self) -> bool {
89        *self == FREQ_A::_1067K
90    }
91    #[doc = "Checks if the value of the field is `_1231K`"]
92    #[inline(always)]
93    pub fn is_1231k(&self) -> bool {
94        *self == FREQ_A::_1231K
95    }
96    #[doc = "Checks if the value of the field is `_1280K`"]
97    #[inline(always)]
98    pub fn is_1280k(&self) -> bool {
99        *self == FREQ_A::_1280K
100    }
101    #[doc = "Checks if the value of the field is `_1333K`"]
102    #[inline(always)]
103    pub fn is_1333k(&self) -> bool {
104        *self == FREQ_A::_1333K
105    }
106}
107#[doc = "Field `FREQ` writer - PDM_CLK frequency"]
108pub type FREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PDMCLKCTRL_SPEC, u32, FREQ_A, 32, O>;
109impl<'a, const O: u8> FREQ_W<'a, O> {
110    #[doc = "PDM_CLK = 32 MHz / 32 = 1.000 MHz"]
111    #[inline(always)]
112    pub fn _1000k(self) -> &'a mut W {
113        self.variant(FREQ_A::_1000K)
114    }
115    #[doc = "PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64."]
116    #[inline(always)]
117    pub fn default(self) -> &'a mut W {
118        self.variant(FREQ_A::DEFAULT)
119    }
120    #[doc = "PDM_CLK = 32 MHz / 30 = 1.067 MHz"]
121    #[inline(always)]
122    pub fn _1067k(self) -> &'a mut W {
123        self.variant(FREQ_A::_1067K)
124    }
125    #[doc = "PDM_CLK = 32 MHz / 26 = 1.231 MHz"]
126    #[inline(always)]
127    pub fn _1231k(self) -> &'a mut W {
128        self.variant(FREQ_A::_1231K)
129    }
130    #[doc = "PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80."]
131    #[inline(always)]
132    pub fn _1280k(self) -> &'a mut W {
133        self.variant(FREQ_A::_1280K)
134    }
135    #[doc = "PDM_CLK = 32 MHz / 24 = 1.333 MHz"]
136    #[inline(always)]
137    pub fn _1333k(self) -> &'a mut W {
138        self.variant(FREQ_A::_1333K)
139    }
140}
141impl R {
142    #[doc = "Bits 0:31 - PDM_CLK frequency"]
143    #[inline(always)]
144    pub fn freq(&self) -> FREQ_R {
145        FREQ_R::new(self.bits)
146    }
147}
148impl W {
149    #[doc = "Bits 0:31 - PDM_CLK frequency"]
150    #[inline(always)]
151    pub fn freq(&mut self) -> FREQ_W<0> {
152        FREQ_W::new(self)
153    }
154    #[doc = "Writes raw bits to the register."]
155    #[inline(always)]
156    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
157        self.0.bits(bits);
158        self
159    }
160}
161#[doc = "PDM clock generator control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdmclkctrl](index.html) module"]
162pub struct PDMCLKCTRL_SPEC;
163impl crate::RegisterSpec for PDMCLKCTRL_SPEC {
164    type Ux = u32;
165}
166#[doc = "`read()` method returns [pdmclkctrl::R](R) reader structure"]
167impl crate::Readable for PDMCLKCTRL_SPEC {
168    type Reader = R;
169}
170#[doc = "`write(|w| ..)` method takes [pdmclkctrl::W](W) writer structure"]
171impl crate::Writable for PDMCLKCTRL_SPEC {
172    type Writer = W;
173}
174#[doc = "`reset()` method sets PDMCLKCTRL to value 0x0840_0000"]
175impl crate::Resettable for PDMCLKCTRL_SPEC {
176    #[inline(always)]
177    fn reset_value() -> Self::Ux {
178        0x0840_0000
179    }
180}
nrf52840_pac/pdm/pdmclkctrl.rs

nrf52840_pac/pdm/
pdmclkctrl.rs
