1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
#[doc = "SRC"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "SRC Control Register"]
    pub SCR: crate::RWRegister<u32>,
    #[doc = "SRC Boot Mode Register 1"]
    pub SBMR1: crate::RORegister<u32>,
    #[doc = "SRC Reset Status Register"]
    pub SRSR: crate::RWRegister<u32>,
    _reserved0: [u8; 0x10],
    #[doc = "SRC Boot Mode Register 2"]
    pub SBMR2: crate::RORegister<u32>,
    #[doc = "SRC General Purpose Register 1"]
    pub GPR1: crate::RWRegister<u32>,
    #[doc = "SRC General Purpose Register 2"]
    pub GPR2: crate::RWRegister<u32>,
    #[doc = "SRC General Purpose Register 3"]
    pub GPR3: crate::RWRegister<u32>,
    #[doc = "SRC General Purpose Register 4"]
    pub GPR4: crate::RWRegister<u32>,
    #[doc = "SRC General Purpose Register 5"]
    pub GPR5: crate::RWRegister<u32>,
    #[doc = "SRC General Purpose Register 6"]
    pub GPR6: crate::RWRegister<u32>,
    #[doc = "SRC General Purpose Register 7"]
    pub GPR7: crate::RWRegister<u32>,
    #[doc = "SRC General Purpose Register 8"]
    pub GPR8: crate::RWRegister<u32>,
    #[doc = "SRC General Purpose Register 9"]
    pub GPR9: crate::RORegister<u32>,
    #[doc = "SRC General Purpose Register 10"]
    pub GPR10: crate::RWRegister<u32>,
}
#[doc = "SRC Control Register"]
pub mod SCR {
    #[doc = "lockup reset enable bit"]
    pub mod LOCKUP_RST {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "disabled"]
            pub const LOCKUP_RST_0: u32 = 0;
            #[doc = "enabled"]
            pub const LOCKUP_RST_1: u32 = 0x01;
        }
    }
    #[doc = "Mask wdog_rst_b source"]
    pub mod MASK_WDOG_RST {
        pub const offset: u32 = 7;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "wdog_rst_b is masked"]
            pub const MASK_WDOG_RST_5: u32 = 0x05;
            #[doc = "wdog_rst_b is not masked (default)"]
            pub const MASK_WDOG_RST_10: u32 = 0x0a;
        }
    }
    #[doc = "Software reset for core0 only"]
    pub mod CORE0_RST {
        pub const offset: u32 = 13;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "do not assert core0 reset"]
            pub const CORE0_RST_0: u32 = 0;
            #[doc = "assert core0 reset"]
            pub const CORE0_RST_1: u32 = 0x01;
        }
    }
    #[doc = "Software reset for core0 debug only"]
    pub mod CORE0_DBG_RST {
        pub const offset: u32 = 17;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "do not assert core0 debug reset"]
            pub const CORE0_DBG_RST_0: u32 = 0;
            #[doc = "assert core0 debug reset"]
            pub const CORE0_DBG_RST_1: u32 = 0x01;
        }
    }
    #[doc = "Do not assert debug resets after power gating event of core"]
    pub mod DBG_RST_MSK_PG {
        pub const offset: u32 = 25;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "do not mask core debug resets (debug resets will be asserted after power gating event)"]
            pub const DBG_RST_MSK_PG_0: u32 = 0;
            #[doc = "mask core debug resets (debug resets won't be asserted after power gating event)"]
            pub const DBG_RST_MSK_PG_1: u32 = 0x01;
        }
    }
    #[doc = "Mask wdog3_rst_b source"]
    pub mod MASK_WDOG3_RST {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "wdog3_rst_b is masked"]
            pub const MASK_WDOG3_RST_5: u32 = 0x05;
            #[doc = "wdog3_rst_b is not masked"]
            pub const MASK_WDOG3_RST_10: u32 = 0x0a;
        }
    }
}
#[doc = "SRC Boot Mode Register 1"]
pub mod SBMR1 {
    #[doc = "Refer to fusemap."]
    pub mod BOOT_CFG1 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Refer to fusemap."]
    pub mod BOOT_CFG2 {
        pub const offset: u32 = 8;
        pub const mask: u32 = 0xff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Refer to fusemap."]
    pub mod BOOT_CFG3 {
        pub const offset: u32 = 16;
        pub const mask: u32 = 0xff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Refer to fusemap."]
    pub mod BOOT_CFG4 {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0xff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SRC Reset Status Register"]
pub mod SRSR {
    #[doc = "Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)"]
    pub mod IPP_RESET_B {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Reset is not a result of ipp_reset_b pin."]
            pub const IPP_RESET_B_0: u32 = 0;
            #[doc = "Reset is a result of ipp_reset_b pin."]
            pub const IPP_RESET_B_1: u32 = 0x01;
        }
    }
    #[doc = "Indicates a reset has been caused by CPU lockup."]
    #[deprecated(since = "0.5.1", note = "Use LOCKUP_SYSRESETREQ")]
    pub mod LOCKUP {
        pub use super::LOCKUP_SYSRESETREQ::*;
    }
    #[doc = "Indicates a reset has been caused by CPU lockup."]
    pub mod LOCKUP_SYSRESETREQ {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Reset is not a result of the mentioned case."]
            pub const LOCKUP_0: u32 = 0;
            #[doc = "Reset is a result of the mentioned case."]
            pub const LOCKUP_1: u32 = 0x01;
        }
    }
    #[doc = "Indicates whether the reset was the result of the csu_reset_b input."]
    pub mod CSU_RESET_B {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Reset is not a result of the csu_reset_b event."]
            pub const CSU_RESET_B_0: u32 = 0;
            #[doc = "Reset is a result of the csu_reset_b event."]
            pub const CSU_RESET_B_1: u32 = 0x01;
        }
    }
    #[doc = "Indicates whether the reset was the result of the ipp_user_reset_b qualified reset."]
    pub mod IPP_USER_RESET_B {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Reset is not a result of the ipp_user_reset_b qualified as COLD reset event."]
            pub const IPP_USER_RESET_B_0: u32 = 0;
            #[doc = "Reset is a result of the ipp_user_reset_b qualified as COLD reset event."]
            pub const IPP_USER_RESET_B_1: u32 = 0x01;
        }
    }
    #[doc = "IC Watchdog Time-out reset"]
    pub mod WDOG_RST_B {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Reset is not a result of the watchdog time-out event."]
            pub const WDOG_RST_B_0: u32 = 0;
            #[doc = "Reset is a result of the watchdog time-out event."]
            pub const WDOG_RST_B_1: u32 = 0x01;
        }
    }
    #[doc = "HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG."]
    pub mod JTAG_RST_B {
        pub const offset: u32 = 5;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Reset is not a result of HIGH-Z reset from JTAG."]
            pub const JTAG_RST_B_0: u32 = 0;
            #[doc = "Reset is a result of HIGH-Z reset from JTAG."]
            pub const JTAG_RST_B_1: u32 = 0x01;
        }
    }
    #[doc = "JTAG software reset"]
    pub mod JTAG_SW_RST {
        pub const offset: u32 = 6;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Reset is not a result of the mentioned case."]
            pub const JTAG_SW_RST_0: u32 = 0;
            #[doc = "Reset is not a result of the mentioned case."]
            pub const JTAG_SW_RST_1: u32 = 0x01;
        }
    }
    #[doc = "IC Watchdog3 Time-out reset"]
    pub mod WDOG3_RST_B {
        pub const offset: u32 = 7;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Reset is not a result of the watchdog3 time-out event."]
            pub const WDOG3_RST_B_0: u32 = 0;
            #[doc = "Reset is a result of the watchdog3 time-out event."]
            pub const WDOG3_RST_B_1: u32 = 0x01;
        }
    }
    #[doc = "Temper Sensor software reset"]
    pub mod TEMPSENSE_RST_B {
        pub const offset: u32 = 8;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Reset is not a result of software reset from Temperature Sensor."]
            pub const TEMPSENSE_RST_B_0: u32 = 0;
            #[doc = "Reset is a result of software reset from Temperature Sensor."]
            pub const TEMPSENSE_RST_B_1: u32 = 0x01;
        }
    }
}
#[doc = "SRC Boot Mode Register 2"]
pub mod SBMR2 {
    #[doc = "SECONFIG\\[1\\] shows the state of the SECONFIG\\[1\\] fuse"]
    pub mod SEC_CONFIG {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "DIR_BT_DIS shows the state of the DIR_BT_DIS fuse"]
    pub mod DIR_BT_DIS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse"]
    pub mod BT_FUSE_SEL {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "BMOD\\[1:0\\] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B"]
    pub mod BMOD {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SRC General Purpose Register 1"]
pub mod GPR1 {
    #[doc = "Holds entry function for core0 for waking-up from low power mode"]
    pub mod PERSISTENT_ENTRY0 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SRC General Purpose Register 2"]
pub mod GPR2 {
    #[doc = "Holds argument of entry function for core0 for waking-up from low power mode"]
    pub mod PERSISTENT_ARG0 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SRC General Purpose Register 10"]
pub mod GPR10 {
    #[doc = "This field identifies which image must be used - 0/1/2/3"]
    pub mod PERSIST_REDUNDANT_BOOT {
        pub const offset: u32 = 26;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "This bit identifies which image must be used - primary and secondary"]
    pub mod PERSIST_SECONDARY_BOOT {
        pub const offset: u32 = 30;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}