imxrt_ral/blocks/imxrt1011/
src.rs1#[doc = "SRC"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "SRC Control Register"]
5 pub SCR: crate::RWRegister<u32>,
6 #[doc = "SRC Boot Mode Register 1"]
7 pub SBMR1: crate::RORegister<u32>,
8 #[doc = "SRC Reset Status Register"]
9 pub SRSR: crate::RWRegister<u32>,
10 _reserved0: [u8; 0x10],
11 #[doc = "SRC Boot Mode Register 2"]
12 pub SBMR2: crate::RORegister<u32>,
13 #[doc = "SRC General Purpose Register 1"]
14 pub GPR1: crate::RWRegister<u32>,
15 #[doc = "SRC General Purpose Register 2"]
16 pub GPR2: crate::RWRegister<u32>,
17 #[doc = "SRC General Purpose Register 3"]
18 pub GPR3: crate::RWRegister<u32>,
19 #[doc = "SRC General Purpose Register 4"]
20 pub GPR4: crate::RWRegister<u32>,
21 #[doc = "SRC General Purpose Register 5"]
22 pub GPR5: crate::RWRegister<u32>,
23 #[doc = "SRC General Purpose Register 6"]
24 pub GPR6: crate::RWRegister<u32>,
25 #[doc = "SRC General Purpose Register 7"]
26 pub GPR7: crate::RWRegister<u32>,
27 #[doc = "SRC General Purpose Register 8"]
28 pub GPR8: crate::RWRegister<u32>,
29 #[doc = "SRC General Purpose Register 9"]
30 pub GPR9: crate::RORegister<u32>,
31 #[doc = "SRC General Purpose Register 10"]
32 pub GPR10: crate::RWRegister<u32>,
33}
34#[doc = "SRC Control Register"]
35pub mod SCR {
36 #[doc = "lockup reset enable bit"]
37 pub mod LOCKUP_RST {
38 pub const offset: u32 = 4;
39 pub const mask: u32 = 0x01 << offset;
40 pub mod R {}
41 pub mod W {}
42 pub mod RW {
43 #[doc = "disabled"]
44 pub const LOCKUP_RST_0: u32 = 0;
45 #[doc = "enabled"]
46 pub const LOCKUP_RST_1: u32 = 0x01;
47 }
48 }
49 #[doc = "Mask wdog_rst_b source"]
50 pub mod MASK_WDOG_RST {
51 pub const offset: u32 = 7;
52 pub const mask: u32 = 0x0f << offset;
53 pub mod R {}
54 pub mod W {}
55 pub mod RW {
56 #[doc = "wdog_rst_b is masked"]
57 pub const MASK_WDOG_RST_5: u32 = 0x05;
58 #[doc = "wdog_rst_b is not masked (default)"]
59 pub const MASK_WDOG_RST_10: u32 = 0x0a;
60 }
61 }
62 #[doc = "Software reset for core0 only"]
63 pub mod CORE0_RST {
64 pub const offset: u32 = 13;
65 pub const mask: u32 = 0x01 << offset;
66 pub mod R {}
67 pub mod W {}
68 pub mod RW {
69 #[doc = "do not assert core0 reset"]
70 pub const CORE0_RST_0: u32 = 0;
71 #[doc = "assert core0 reset"]
72 pub const CORE0_RST_1: u32 = 0x01;
73 }
74 }
75 #[doc = "Software reset for core0 debug only"]
76 pub mod CORE0_DBG_RST {
77 pub const offset: u32 = 17;
78 pub const mask: u32 = 0x01 << offset;
79 pub mod R {}
80 pub mod W {}
81 pub mod RW {
82 #[doc = "do not assert core0 debug reset"]
83 pub const CORE0_DBG_RST_0: u32 = 0;
84 #[doc = "assert core0 debug reset"]
85 pub const CORE0_DBG_RST_1: u32 = 0x01;
86 }
87 }
88 #[doc = "Do not assert debug resets after power gating event of core"]
89 pub mod DBG_RST_MSK_PG {
90 pub const offset: u32 = 25;
91 pub const mask: u32 = 0x01 << offset;
92 pub mod R {}
93 pub mod W {}
94 pub mod RW {
95 #[doc = "do not mask core debug resets (debug resets will be asserted after power gating event)"]
96 pub const DBG_RST_MSK_PG_0: u32 = 0;
97 #[doc = "mask core debug resets (debug resets won't be asserted after power gating event)"]
98 pub const DBG_RST_MSK_PG_1: u32 = 0x01;
99 }
100 }
101 #[doc = "Mask wdog3_rst_b source"]
102 pub mod MASK_WDOG3_RST {
103 pub const offset: u32 = 28;
104 pub const mask: u32 = 0x0f << offset;
105 pub mod R {}
106 pub mod W {}
107 pub mod RW {
108 #[doc = "wdog3_rst_b is masked"]
109 pub const MASK_WDOG3_RST_5: u32 = 0x05;
110 #[doc = "wdog3_rst_b is not masked"]
111 pub const MASK_WDOG3_RST_10: u32 = 0x0a;
112 }
113 }
114}
115#[doc = "SRC Boot Mode Register 1"]
116pub mod SBMR1 {
117 #[doc = "Refer to fusemap."]
118 pub mod BOOT_CFG1 {
119 pub const offset: u32 = 0;
120 pub const mask: u32 = 0xff << offset;
121 pub mod R {}
122 pub mod W {}
123 pub mod RW {}
124 }
125 #[doc = "Refer to fusemap."]
126 pub mod BOOT_CFG2 {
127 pub const offset: u32 = 8;
128 pub const mask: u32 = 0xff << offset;
129 pub mod R {}
130 pub mod W {}
131 pub mod RW {}
132 }
133 #[doc = "Refer to fusemap."]
134 pub mod BOOT_CFG3 {
135 pub const offset: u32 = 16;
136 pub const mask: u32 = 0xff << offset;
137 pub mod R {}
138 pub mod W {}
139 pub mod RW {}
140 }
141 #[doc = "Refer to fusemap."]
142 pub mod BOOT_CFG4 {
143 pub const offset: u32 = 24;
144 pub const mask: u32 = 0xff << offset;
145 pub mod R {}
146 pub mod W {}
147 pub mod RW {}
148 }
149}
150#[doc = "SRC Reset Status Register"]
151pub mod SRSR {
152 #[doc = "Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)"]
153 pub mod IPP_RESET_B {
154 pub const offset: u32 = 0;
155 pub const mask: u32 = 0x01 << offset;
156 pub mod R {}
157 pub mod W {}
158 pub mod RW {
159 #[doc = "Reset is not a result of ipp_reset_b pin."]
160 pub const IPP_RESET_B_0: u32 = 0;
161 #[doc = "Reset is a result of ipp_reset_b pin."]
162 pub const IPP_RESET_B_1: u32 = 0x01;
163 }
164 }
165 #[doc = "Indicates a reset has been caused by CPU lockup."]
166 pub mod LOCKUP_SYSRESETREQ {
167 pub const offset: u32 = 1;
168 pub const mask: u32 = 0x01 << offset;
169 pub mod R {}
170 pub mod W {}
171 pub mod RW {
172 #[doc = "Reset is not a result of the mentioned case."]
173 pub const LOCKUP_0: u32 = 0;
174 #[doc = "Reset is a result of the mentioned case."]
175 pub const LOCKUP_1: u32 = 0x01;
176 }
177 }
178 #[doc = "Indicates whether the reset was the result of the csu_reset_b input."]
179 pub mod CSU_RESET_B {
180 pub const offset: u32 = 2;
181 pub const mask: u32 = 0x01 << offset;
182 pub mod R {}
183 pub mod W {}
184 pub mod RW {
185 #[doc = "Reset is not a result of the csu_reset_b event."]
186 pub const CSU_RESET_B_0: u32 = 0;
187 #[doc = "Reset is a result of the csu_reset_b event."]
188 pub const CSU_RESET_B_1: u32 = 0x01;
189 }
190 }
191 #[doc = "Indicates whether the reset was the result of the ipp_user_reset_b qualified reset."]
192 pub mod IPP_USER_RESET_B {
193 pub const offset: u32 = 3;
194 pub const mask: u32 = 0x01 << offset;
195 pub mod R {}
196 pub mod W {}
197 pub mod RW {
198 #[doc = "Reset is not a result of the ipp_user_reset_b qualified as COLD reset event."]
199 pub const IPP_USER_RESET_B_0: u32 = 0;
200 #[doc = "Reset is a result of the ipp_user_reset_b qualified as COLD reset event."]
201 pub const IPP_USER_RESET_B_1: u32 = 0x01;
202 }
203 }
204 #[doc = "IC Watchdog Time-out reset"]
205 pub mod WDOG_RST_B {
206 pub const offset: u32 = 4;
207 pub const mask: u32 = 0x01 << offset;
208 pub mod R {}
209 pub mod W {}
210 pub mod RW {
211 #[doc = "Reset is not a result of the watchdog time-out event."]
212 pub const WDOG_RST_B_0: u32 = 0;
213 #[doc = "Reset is a result of the watchdog time-out event."]
214 pub const WDOG_RST_B_1: u32 = 0x01;
215 }
216 }
217 #[doc = "HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG."]
218 pub mod JTAG_RST_B {
219 pub const offset: u32 = 5;
220 pub const mask: u32 = 0x01 << offset;
221 pub mod R {}
222 pub mod W {}
223 pub mod RW {
224 #[doc = "Reset is not a result of HIGH-Z reset from JTAG."]
225 pub const JTAG_RST_B_0: u32 = 0;
226 #[doc = "Reset is a result of HIGH-Z reset from JTAG."]
227 pub const JTAG_RST_B_1: u32 = 0x01;
228 }
229 }
230 #[doc = "JTAG software reset"]
231 pub mod JTAG_SW_RST {
232 pub const offset: u32 = 6;
233 pub const mask: u32 = 0x01 << offset;
234 pub mod R {}
235 pub mod W {}
236 pub mod RW {
237 #[doc = "Reset is not a result of the mentioned case."]
238 pub const JTAG_SW_RST_0: u32 = 0;
239 #[doc = "Reset is not a result of the mentioned case."]
240 pub const JTAG_SW_RST_1: u32 = 0x01;
241 }
242 }
243 #[doc = "IC Watchdog3 Time-out reset"]
244 pub mod WDOG3_RST_B {
245 pub const offset: u32 = 7;
246 pub const mask: u32 = 0x01 << offset;
247 pub mod R {}
248 pub mod W {}
249 pub mod RW {
250 #[doc = "Reset is not a result of the watchdog3 time-out event."]
251 pub const WDOG3_RST_B_0: u32 = 0;
252 #[doc = "Reset is a result of the watchdog3 time-out event."]
253 pub const WDOG3_RST_B_1: u32 = 0x01;
254 }
255 }
256 #[doc = "Temper Sensor software reset"]
257 pub mod TEMPSENSE_RST_B {
258 pub const offset: u32 = 8;
259 pub const mask: u32 = 0x01 << offset;
260 pub mod R {}
261 pub mod W {}
262 pub mod RW {
263 #[doc = "Reset is not a result of software reset from Temperature Sensor."]
264 pub const TEMPSENSE_RST_B_0: u32 = 0;
265 #[doc = "Reset is a result of software reset from Temperature Sensor."]
266 pub const TEMPSENSE_RST_B_1: u32 = 0x01;
267 }
268 }
269}
270#[doc = "SRC Boot Mode Register 2"]
271pub mod SBMR2 {
272 #[doc = "SECONFIG\\[1\\] shows the state of the SECONFIG\\[1\\] fuse"]
273 pub mod SEC_CONFIG {
274 pub const offset: u32 = 0;
275 pub const mask: u32 = 0x03 << offset;
276 pub mod R {}
277 pub mod W {}
278 pub mod RW {}
279 }
280 #[doc = "DIR_BT_DIS shows the state of the DIR_BT_DIS fuse"]
281 pub mod DIR_BT_DIS {
282 pub const offset: u32 = 3;
283 pub const mask: u32 = 0x01 << offset;
284 pub mod R {}
285 pub mod W {}
286 pub mod RW {}
287 }
288 #[doc = "BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse"]
289 pub mod BT_FUSE_SEL {
290 pub const offset: u32 = 4;
291 pub const mask: u32 = 0x01 << offset;
292 pub mod R {}
293 pub mod W {}
294 pub mod RW {}
295 }
296 #[doc = "BMOD\\[1:0\\] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B"]
297 pub mod BMOD {
298 pub const offset: u32 = 24;
299 pub const mask: u32 = 0x03 << offset;
300 pub mod R {}
301 pub mod W {}
302 pub mod RW {}
303 }
304}
305#[doc = "SRC General Purpose Register 1"]
306pub mod GPR1 {
307 #[doc = "Holds entry function for core0 for waking-up from low power mode"]
308 pub mod PERSISTENT_ENTRY0 {
309 pub const offset: u32 = 0;
310 pub const mask: u32 = 0xffff_ffff << offset;
311 pub mod R {}
312 pub mod W {}
313 pub mod RW {}
314 }
315}
316#[doc = "SRC General Purpose Register 2"]
317pub mod GPR2 {
318 #[doc = "Holds argument of entry function for core0 for waking-up from low power mode"]
319 pub mod PERSISTENT_ARG0 {
320 pub const offset: u32 = 0;
321 pub const mask: u32 = 0xffff_ffff << offset;
322 pub mod R {}
323 pub mod W {}
324 pub mod RW {}
325 }
326}
327#[doc = "SRC General Purpose Register 10"]
328pub mod GPR10 {
329 #[doc = "This field identifies which image must be used - 0/1/2/3"]
330 pub mod PERSIST_REDUNDANT_BOOT {
331 pub const offset: u32 = 26;
332 pub const mask: u32 = 0x03 << offset;
333 pub mod R {}
334 pub mod W {}
335 pub mod RW {}
336 }
337 #[doc = "This bit identifies which image must be used - primary and secondary"]
338 pub mod PERSIST_SECONDARY_BOOT {
339 pub const offset: u32 = 30;
340 pub const mask: u32 = 0x01 << offset;
341 pub mod R {}
342 pub mod W {}
343 pub mod RW {}
344 }
345}