imxrt_ral/blocks/imxrt1011/
src.rs

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1#[doc = "SRC"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "SRC Control Register"]
5    pub SCR: crate::RWRegister<u32>,
6    #[doc = "SRC Boot Mode Register 1"]
7    pub SBMR1: crate::RORegister<u32>,
8    #[doc = "SRC Reset Status Register"]
9    pub SRSR: crate::RWRegister<u32>,
10    _reserved0: [u8; 0x10],
11    #[doc = "SRC Boot Mode Register 2"]
12    pub SBMR2: crate::RORegister<u32>,
13    #[doc = "SRC General Purpose Register 1"]
14    pub GPR1: crate::RWRegister<u32>,
15    #[doc = "SRC General Purpose Register 2"]
16    pub GPR2: crate::RWRegister<u32>,
17    #[doc = "SRC General Purpose Register 3"]
18    pub GPR3: crate::RWRegister<u32>,
19    #[doc = "SRC General Purpose Register 4"]
20    pub GPR4: crate::RWRegister<u32>,
21    #[doc = "SRC General Purpose Register 5"]
22    pub GPR5: crate::RWRegister<u32>,
23    #[doc = "SRC General Purpose Register 6"]
24    pub GPR6: crate::RWRegister<u32>,
25    #[doc = "SRC General Purpose Register 7"]
26    pub GPR7: crate::RWRegister<u32>,
27    #[doc = "SRC General Purpose Register 8"]
28    pub GPR8: crate::RWRegister<u32>,
29    #[doc = "SRC General Purpose Register 9"]
30    pub GPR9: crate::RORegister<u32>,
31    #[doc = "SRC General Purpose Register 10"]
32    pub GPR10: crate::RWRegister<u32>,
33}
34#[doc = "SRC Control Register"]
35pub mod SCR {
36    #[doc = "lockup reset enable bit"]
37    pub mod LOCKUP_RST {
38        pub const offset: u32 = 4;
39        pub const mask: u32 = 0x01 << offset;
40        pub mod R {}
41        pub mod W {}
42        pub mod RW {
43            #[doc = "disabled"]
44            pub const LOCKUP_RST_0: u32 = 0;
45            #[doc = "enabled"]
46            pub const LOCKUP_RST_1: u32 = 0x01;
47        }
48    }
49    #[doc = "Mask wdog_rst_b source"]
50    pub mod MASK_WDOG_RST {
51        pub const offset: u32 = 7;
52        pub const mask: u32 = 0x0f << offset;
53        pub mod R {}
54        pub mod W {}
55        pub mod RW {
56            #[doc = "wdog_rst_b is masked"]
57            pub const MASK_WDOG_RST_5: u32 = 0x05;
58            #[doc = "wdog_rst_b is not masked (default)"]
59            pub const MASK_WDOG_RST_10: u32 = 0x0a;
60        }
61    }
62    #[doc = "Software reset for core0 only"]
63    pub mod CORE0_RST {
64        pub const offset: u32 = 13;
65        pub const mask: u32 = 0x01 << offset;
66        pub mod R {}
67        pub mod W {}
68        pub mod RW {
69            #[doc = "do not assert core0 reset"]
70            pub const CORE0_RST_0: u32 = 0;
71            #[doc = "assert core0 reset"]
72            pub const CORE0_RST_1: u32 = 0x01;
73        }
74    }
75    #[doc = "Software reset for core0 debug only"]
76    pub mod CORE0_DBG_RST {
77        pub const offset: u32 = 17;
78        pub const mask: u32 = 0x01 << offset;
79        pub mod R {}
80        pub mod W {}
81        pub mod RW {
82            #[doc = "do not assert core0 debug reset"]
83            pub const CORE0_DBG_RST_0: u32 = 0;
84            #[doc = "assert core0 debug reset"]
85            pub const CORE0_DBG_RST_1: u32 = 0x01;
86        }
87    }
88    #[doc = "Do not assert debug resets after power gating event of core"]
89    pub mod DBG_RST_MSK_PG {
90        pub const offset: u32 = 25;
91        pub const mask: u32 = 0x01 << offset;
92        pub mod R {}
93        pub mod W {}
94        pub mod RW {
95            #[doc = "do not mask core debug resets (debug resets will be asserted after power gating event)"]
96            pub const DBG_RST_MSK_PG_0: u32 = 0;
97            #[doc = "mask core debug resets (debug resets won't be asserted after power gating event)"]
98            pub const DBG_RST_MSK_PG_1: u32 = 0x01;
99        }
100    }
101    #[doc = "Mask wdog3_rst_b source"]
102    pub mod MASK_WDOG3_RST {
103        pub const offset: u32 = 28;
104        pub const mask: u32 = 0x0f << offset;
105        pub mod R {}
106        pub mod W {}
107        pub mod RW {
108            #[doc = "wdog3_rst_b is masked"]
109            pub const MASK_WDOG3_RST_5: u32 = 0x05;
110            #[doc = "wdog3_rst_b is not masked"]
111            pub const MASK_WDOG3_RST_10: u32 = 0x0a;
112        }
113    }
114}
115#[doc = "SRC Boot Mode Register 1"]
116pub mod SBMR1 {
117    #[doc = "Refer to fusemap."]
118    pub mod BOOT_CFG1 {
119        pub const offset: u32 = 0;
120        pub const mask: u32 = 0xff << offset;
121        pub mod R {}
122        pub mod W {}
123        pub mod RW {}
124    }
125    #[doc = "Refer to fusemap."]
126    pub mod BOOT_CFG2 {
127        pub const offset: u32 = 8;
128        pub const mask: u32 = 0xff << offset;
129        pub mod R {}
130        pub mod W {}
131        pub mod RW {}
132    }
133    #[doc = "Refer to fusemap."]
134    pub mod BOOT_CFG3 {
135        pub const offset: u32 = 16;
136        pub const mask: u32 = 0xff << offset;
137        pub mod R {}
138        pub mod W {}
139        pub mod RW {}
140    }
141    #[doc = "Refer to fusemap."]
142    pub mod BOOT_CFG4 {
143        pub const offset: u32 = 24;
144        pub const mask: u32 = 0xff << offset;
145        pub mod R {}
146        pub mod W {}
147        pub mod RW {}
148    }
149}
150#[doc = "SRC Reset Status Register"]
151pub mod SRSR {
152    #[doc = "Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)"]
153    pub mod IPP_RESET_B {
154        pub const offset: u32 = 0;
155        pub const mask: u32 = 0x01 << offset;
156        pub mod R {}
157        pub mod W {}
158        pub mod RW {
159            #[doc = "Reset is not a result of ipp_reset_b pin."]
160            pub const IPP_RESET_B_0: u32 = 0;
161            #[doc = "Reset is a result of ipp_reset_b pin."]
162            pub const IPP_RESET_B_1: u32 = 0x01;
163        }
164    }
165    #[doc = "Indicates a reset has been caused by CPU lockup."]
166    #[deprecated(since = "0.5.1", note = "Use LOCKUP_SYSRESETREQ")]
167    pub mod LOCKUP {
168        pub use super::LOCKUP_SYSRESETREQ::*;
169    }
170    #[doc = "Indicates a reset has been caused by CPU lockup."]
171    pub mod LOCKUP_SYSRESETREQ {
172        pub const offset: u32 = 1;
173        pub const mask: u32 = 0x01 << offset;
174        pub mod R {}
175        pub mod W {}
176        pub mod RW {
177            #[doc = "Reset is not a result of the mentioned case."]
178            pub const LOCKUP_0: u32 = 0;
179            #[doc = "Reset is a result of the mentioned case."]
180            pub const LOCKUP_1: u32 = 0x01;
181        }
182    }
183    #[doc = "Indicates whether the reset was the result of the csu_reset_b input."]
184    pub mod CSU_RESET_B {
185        pub const offset: u32 = 2;
186        pub const mask: u32 = 0x01 << offset;
187        pub mod R {}
188        pub mod W {}
189        pub mod RW {
190            #[doc = "Reset is not a result of the csu_reset_b event."]
191            pub const CSU_RESET_B_0: u32 = 0;
192            #[doc = "Reset is a result of the csu_reset_b event."]
193            pub const CSU_RESET_B_1: u32 = 0x01;
194        }
195    }
196    #[doc = "Indicates whether the reset was the result of the ipp_user_reset_b qualified reset."]
197    pub mod IPP_USER_RESET_B {
198        pub const offset: u32 = 3;
199        pub const mask: u32 = 0x01 << offset;
200        pub mod R {}
201        pub mod W {}
202        pub mod RW {
203            #[doc = "Reset is not a result of the ipp_user_reset_b qualified as COLD reset event."]
204            pub const IPP_USER_RESET_B_0: u32 = 0;
205            #[doc = "Reset is a result of the ipp_user_reset_b qualified as COLD reset event."]
206            pub const IPP_USER_RESET_B_1: u32 = 0x01;
207        }
208    }
209    #[doc = "IC Watchdog Time-out reset"]
210    pub mod WDOG_RST_B {
211        pub const offset: u32 = 4;
212        pub const mask: u32 = 0x01 << offset;
213        pub mod R {}
214        pub mod W {}
215        pub mod RW {
216            #[doc = "Reset is not a result of the watchdog time-out event."]
217            pub const WDOG_RST_B_0: u32 = 0;
218            #[doc = "Reset is a result of the watchdog time-out event."]
219            pub const WDOG_RST_B_1: u32 = 0x01;
220        }
221    }
222    #[doc = "HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG."]
223    pub mod JTAG_RST_B {
224        pub const offset: u32 = 5;
225        pub const mask: u32 = 0x01 << offset;
226        pub mod R {}
227        pub mod W {}
228        pub mod RW {
229            #[doc = "Reset is not a result of HIGH-Z reset from JTAG."]
230            pub const JTAG_RST_B_0: u32 = 0;
231            #[doc = "Reset is a result of HIGH-Z reset from JTAG."]
232            pub const JTAG_RST_B_1: u32 = 0x01;
233        }
234    }
235    #[doc = "JTAG software reset"]
236    pub mod JTAG_SW_RST {
237        pub const offset: u32 = 6;
238        pub const mask: u32 = 0x01 << offset;
239        pub mod R {}
240        pub mod W {}
241        pub mod RW {
242            #[doc = "Reset is not a result of the mentioned case."]
243            pub const JTAG_SW_RST_0: u32 = 0;
244            #[doc = "Reset is not a result of the mentioned case."]
245            pub const JTAG_SW_RST_1: u32 = 0x01;
246        }
247    }
248    #[doc = "IC Watchdog3 Time-out reset"]
249    pub mod WDOG3_RST_B {
250        pub const offset: u32 = 7;
251        pub const mask: u32 = 0x01 << offset;
252        pub mod R {}
253        pub mod W {}
254        pub mod RW {
255            #[doc = "Reset is not a result of the watchdog3 time-out event."]
256            pub const WDOG3_RST_B_0: u32 = 0;
257            #[doc = "Reset is a result of the watchdog3 time-out event."]
258            pub const WDOG3_RST_B_1: u32 = 0x01;
259        }
260    }
261    #[doc = "Temper Sensor software reset"]
262    pub mod TEMPSENSE_RST_B {
263        pub const offset: u32 = 8;
264        pub const mask: u32 = 0x01 << offset;
265        pub mod R {}
266        pub mod W {}
267        pub mod RW {
268            #[doc = "Reset is not a result of software reset from Temperature Sensor."]
269            pub const TEMPSENSE_RST_B_0: u32 = 0;
270            #[doc = "Reset is a result of software reset from Temperature Sensor."]
271            pub const TEMPSENSE_RST_B_1: u32 = 0x01;
272        }
273    }
274}
275#[doc = "SRC Boot Mode Register 2"]
276pub mod SBMR2 {
277    #[doc = "SECONFIG\\[1\\] shows the state of the SECONFIG\\[1\\] fuse"]
278    pub mod SEC_CONFIG {
279        pub const offset: u32 = 0;
280        pub const mask: u32 = 0x03 << offset;
281        pub mod R {}
282        pub mod W {}
283        pub mod RW {}
284    }
285    #[doc = "DIR_BT_DIS shows the state of the DIR_BT_DIS fuse"]
286    pub mod DIR_BT_DIS {
287        pub const offset: u32 = 3;
288        pub const mask: u32 = 0x01 << offset;
289        pub mod R {}
290        pub mod W {}
291        pub mod RW {}
292    }
293    #[doc = "BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse"]
294    pub mod BT_FUSE_SEL {
295        pub const offset: u32 = 4;
296        pub const mask: u32 = 0x01 << offset;
297        pub mod R {}
298        pub mod W {}
299        pub mod RW {}
300    }
301    #[doc = "BMOD\\[1:0\\] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B"]
302    pub mod BMOD {
303        pub const offset: u32 = 24;
304        pub const mask: u32 = 0x03 << offset;
305        pub mod R {}
306        pub mod W {}
307        pub mod RW {}
308    }
309}
310#[doc = "SRC General Purpose Register 1"]
311pub mod GPR1 {
312    #[doc = "Holds entry function for core0 for waking-up from low power mode"]
313    pub mod PERSISTENT_ENTRY0 {
314        pub const offset: u32 = 0;
315        pub const mask: u32 = 0xffff_ffff << offset;
316        pub mod R {}
317        pub mod W {}
318        pub mod RW {}
319    }
320}
321#[doc = "SRC General Purpose Register 2"]
322pub mod GPR2 {
323    #[doc = "Holds argument of entry function for core0 for waking-up from low power mode"]
324    pub mod PERSISTENT_ARG0 {
325        pub const offset: u32 = 0;
326        pub const mask: u32 = 0xffff_ffff << offset;
327        pub mod R {}
328        pub mod W {}
329        pub mod RW {}
330    }
331}
332#[doc = "SRC General Purpose Register 10"]
333pub mod GPR10 {
334    #[doc = "This field identifies which image must be used - 0/1/2/3"]
335    pub mod PERSIST_REDUNDANT_BOOT {
336        pub const offset: u32 = 26;
337        pub const mask: u32 = 0x03 << offset;
338        pub mod R {}
339        pub mod W {}
340        pub mod RW {}
341    }
342    #[doc = "This bit identifies which image must be used - primary and secondary"]
343    pub mod PERSIST_SECONDARY_BOOT {
344        pub const offset: u32 = 30;
345        pub const mask: u32 = 0x01 << offset;
346        pub mod R {}
347        pub mod W {}
348        pub mod RW {}
349    }
350}
imxrt_ral/blocks/imxrt1011/src.rs

imxrt_ral/blocks/imxrt1011/
src.rs
