rp2040_pac/xip_ctrl/
ctrl.rs

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1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `EN` reader - When 1, enable the cache. When the cache is disabled, all XIP accesses  
6 will go straight to the flash, without querying the cache. When enabled,  
7 cacheable XIP accesses will query the cache, and the flash will  
8 not be accessed if the tag matches and the valid bit is set.  
9
10 If the cache is enabled, cache-as-SRAM accesses have no effect on the  
11 cache data RAM, and will produce a bus error response."]
12pub type EN_R = crate::BitReader;
13#[doc = "Field `EN` writer - When 1, enable the cache. When the cache is disabled, all XIP accesses  
14 will go straight to the flash, without querying the cache. When enabled,  
15 cacheable XIP accesses will query the cache, and the flash will  
16 not be accessed if the tag matches and the valid bit is set.  
17
18 If the cache is enabled, cache-as-SRAM accesses have no effect on the  
19 cache data RAM, and will produce a bus error response."]
20pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ERR_BADWRITE` reader - When 1, writes to any alias other than 0x0 (caching, allocating)  
22 will produce a bus fault. When 0, these writes are silently ignored.  
23 In either case, writes to the 0x0 alias will deallocate on tag match,  
24 as usual."]
25pub type ERR_BADWRITE_R = crate::BitReader;
26#[doc = "Field `ERR_BADWRITE` writer - When 1, writes to any alias other than 0x0 (caching, allocating)  
27 will produce a bus fault. When 0, these writes are silently ignored.  
28 In either case, writes to the 0x0 alias will deallocate on tag match,  
29 as usual."]
30pub type ERR_BADWRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `POWER_DOWN` reader - When 1, the cache memories are powered down. They retain state,  
32 but can not be accessed. This reduces static power dissipation.  
33 Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot  
34 be enabled when powered down.  
35 Cache-as-SRAM accesses will produce a bus error response when  
36 the cache is powered down."]
37pub type POWER_DOWN_R = crate::BitReader;
38#[doc = "Field `POWER_DOWN` writer - When 1, the cache memories are powered down. They retain state,  
39 but can not be accessed. This reduces static power dissipation.  
40 Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot  
41 be enabled when powered down.  
42 Cache-as-SRAM accesses will produce a bus error response when  
43 the cache is powered down."]
44pub type POWER_DOWN_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses  
47 will go straight to the flash, without querying the cache. When enabled,  
48 cacheable XIP accesses will query the cache, and the flash will  
49 not be accessed if the tag matches and the valid bit is set.  
50
51 If the cache is enabled, cache-as-SRAM accesses have no effect on the  
52 cache data RAM, and will produce a bus error response."]
53    #[inline(always)]
54    pub fn en(&self) -> EN_R {
55        EN_R::new((self.bits & 1) != 0)
56    }
57    #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating)  
58 will produce a bus fault. When 0, these writes are silently ignored.  
59 In either case, writes to the 0x0 alias will deallocate on tag match,  
60 as usual."]
61    #[inline(always)]
62    pub fn err_badwrite(&self) -> ERR_BADWRITE_R {
63        ERR_BADWRITE_R::new(((self.bits >> 1) & 1) != 0)
64    }
65    #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state,  
66 but can not be accessed. This reduces static power dissipation.  
67 Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot  
68 be enabled when powered down.  
69 Cache-as-SRAM accesses will produce a bus error response when  
70 the cache is powered down."]
71    #[inline(always)]
72    pub fn power_down(&self) -> POWER_DOWN_R {
73        POWER_DOWN_R::new(((self.bits >> 3) & 1) != 0)
74    }
75}
76impl W {
77    #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses  
78 will go straight to the flash, without querying the cache. When enabled,  
79 cacheable XIP accesses will query the cache, and the flash will  
80 not be accessed if the tag matches and the valid bit is set.  
81
82 If the cache is enabled, cache-as-SRAM accesses have no effect on the  
83 cache data RAM, and will produce a bus error response."]
84    #[inline(always)]
85    #[must_use]
86    pub fn en(&mut self) -> EN_W<CTRL_SPEC> {
87        EN_W::new(self, 0)
88    }
89    #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating)  
90 will produce a bus fault. When 0, these writes are silently ignored.  
91 In either case, writes to the 0x0 alias will deallocate on tag match,  
92 as usual."]
93    #[inline(always)]
94    #[must_use]
95    pub fn err_badwrite(&mut self) -> ERR_BADWRITE_W<CTRL_SPEC> {
96        ERR_BADWRITE_W::new(self, 1)
97    }
98    #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state,  
99 but can not be accessed. This reduces static power dissipation.  
100 Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot  
101 be enabled when powered down.  
102 Cache-as-SRAM accesses will produce a bus error response when  
103 the cache is powered down."]
104    #[inline(always)]
105    #[must_use]
106    pub fn power_down(&mut self) -> POWER_DOWN_W<CTRL_SPEC> {
107        POWER_DOWN_W::new(self, 3)
108    }
109    #[doc = r" Writes raw bits to the register."]
110    #[doc = r""]
111    #[doc = r" # Safety"]
112    #[doc = r""]
113    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
114    #[inline(always)]
115    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
116        self.bits = bits;
117        self
118    }
119}
120#[doc = "Cache control  
121
122You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
123pub struct CTRL_SPEC;
124impl crate::RegisterSpec for CTRL_SPEC {
125    type Ux = u32;
126}
127#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
128impl crate::Readable for CTRL_SPEC {}
129#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
130impl crate::Writable for CTRL_SPEC {
131    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets CTRL to value 0x03"]
135impl crate::Resettable for CTRL_SPEC {
136    const RESET_VALUE: u32 = 0x03;
137}
rp2040_pac/xip_ctrl/ctrl.rs

rp2040_pac/xip_ctrl/
ctrl.rs
