1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0xe010],
5 syst_csr: SYST_CSR,
6 syst_rvr: SYST_RVR,
7 syst_cvr: SYST_CVR,
8 syst_calib: SYST_CALIB,
9 _reserved4: [u8; 0xe0],
10 nvic_iser: NVIC_ISER,
11 _reserved5: [u8; 0x7c],
12 nvic_icer: NVIC_ICER,
13 _reserved6: [u8; 0x7c],
14 nvic_ispr: NVIC_ISPR,
15 _reserved7: [u8; 0x7c],
16 nvic_icpr: NVIC_ICPR,
17 _reserved8: [u8; 0x017c],
18 nvic_ipr0: NVIC_IPR0,
19 nvic_ipr1: NVIC_IPR1,
20 nvic_ipr2: NVIC_IPR2,
21 nvic_ipr3: NVIC_IPR3,
22 nvic_ipr4: NVIC_IPR4,
23 nvic_ipr5: NVIC_IPR5,
24 nvic_ipr6: NVIC_IPR6,
25 nvic_ipr7: NVIC_IPR7,
26 _reserved16: [u8; 0x08e0],
27 cpuid: CPUID,
28 icsr: ICSR,
29 vtor: VTOR,
30 aircr: AIRCR,
31 scr: SCR,
32 ccr: CCR,
33 _reserved22: [u8; 0x04],
34 shpr2: SHPR2,
35 shpr3: SHPR3,
36 shcsr: SHCSR,
37 _reserved25: [u8; 0x68],
38 mpu_type: MPU_TYPE,
39 mpu_ctrl: MPU_CTRL,
40 mpu_rnr: MPU_RNR,
41 mpu_rbar: MPU_RBAR,
42 mpu_rasr: MPU_RASR,
43}
44impl RegisterBlock {
45 #[doc = "0xe010 - Use the SysTick Control and Status Register to enable the SysTick features."]
46 #[inline(always)]
47 pub const fn syst_csr(&self) -> &SYST_CSR {
48 &self.syst_csr
49 }
50 #[doc = "0xe014 - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.
51 To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99."]
52 #[inline(always)]
53 pub const fn syst_rvr(&self) -> &SYST_RVR {
54 &self.syst_rvr
55 }
56 #[doc = "0xe018 - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN."]
57 #[inline(always)]
58 pub const fn syst_cvr(&self) -> &SYST_CVR {
59 &self.syst_cvr
60 }
61 #[doc = "0xe01c - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply."]
62 #[inline(always)]
63 pub const fn syst_calib(&self) -> &SYST_CALIB {
64 &self.syst_calib
65 }
66 #[doc = "0xe100 - Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.
67 If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority."]
68 #[inline(always)]
69 pub const fn nvic_iser(&self) -> &NVIC_ISER {
70 &self.nvic_iser
71 }
72 #[doc = "0xe180 - Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled."]
73 #[inline(always)]
74 pub const fn nvic_icer(&self) -> &NVIC_ICER {
75 &self.nvic_icer
76 }
77 #[doc = "0xe200 - The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending."]
78 #[inline(always)]
79 pub const fn nvic_ispr(&self) -> &NVIC_ISPR {
80 &self.nvic_ispr
81 }
82 #[doc = "0xe280 - Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending."]
83 #[inline(always)]
84 pub const fn nvic_icpr(&self) -> &NVIC_ICPR {
85 &self.nvic_icpr
86 }
87 #[doc = "0xe400 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
88 Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
89 These registers are only word-accessible"]
90 #[inline(always)]
91 pub const fn nvic_ipr0(&self) -> &NVIC_IPR0 {
92 &self.nvic_ipr0
93 }
94 #[doc = "0xe404 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
95 #[inline(always)]
96 pub const fn nvic_ipr1(&self) -> &NVIC_IPR1 {
97 &self.nvic_ipr1
98 }
99 #[doc = "0xe408 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
100 #[inline(always)]
101 pub const fn nvic_ipr2(&self) -> &NVIC_IPR2 {
102 &self.nvic_ipr2
103 }
104 #[doc = "0xe40c - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
105 #[inline(always)]
106 pub const fn nvic_ipr3(&self) -> &NVIC_IPR3 {
107 &self.nvic_ipr3
108 }
109 #[doc = "0xe410 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
110 #[inline(always)]
111 pub const fn nvic_ipr4(&self) -> &NVIC_IPR4 {
112 &self.nvic_ipr4
113 }
114 #[doc = "0xe414 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
115 #[inline(always)]
116 pub const fn nvic_ipr5(&self) -> &NVIC_IPR5 {
117 &self.nvic_ipr5
118 }
119 #[doc = "0xe418 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
120 #[inline(always)]
121 pub const fn nvic_ipr6(&self) -> &NVIC_IPR6 {
122 &self.nvic_ipr6
123 }
124 #[doc = "0xe41c - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
125 #[inline(always)]
126 pub const fn nvic_ipr7(&self) -> &NVIC_IPR7 {
127 &self.nvic_ipr7
128 }
129 #[doc = "0xed00 - Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core."]
130 #[inline(always)]
131 pub const fn cpuid(&self) -> &CPUID {
132 &self.cpuid
133 }
134 #[doc = "0xed04 - Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception."]
135 #[inline(always)]
136 pub const fn icsr(&self) -> &ICSR {
137 &self.icsr
138 }
139 #[doc = "0xed08 - The VTOR holds the vector table offset address."]
140 #[inline(always)]
141 pub const fn vtor(&self) -> &VTOR {
142 &self.vtor
143 }
144 #[doc = "0xed0c - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset."]
145 #[inline(always)]
146 pub const fn aircr(&self) -> &AIRCR {
147 &self.aircr
148 }
149 #[doc = "0xed10 - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states."]
150 #[inline(always)]
151 pub const fn scr(&self) -> &SCR {
152 &self.scr
153 }
154 #[doc = "0xed14 - The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault."]
155 #[inline(always)]
156 pub const fn ccr(&self) -> &CCR {
157 &self.ccr
158 }
159 #[doc = "0xed1c - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall."]
160 #[inline(always)]
161 pub const fn shpr2(&self) -> &SHPR2 {
162 &self.shpr2
163 }
164 #[doc = "0xed20 - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick."]
165 #[inline(always)]
166 pub const fn shpr3(&self) -> &SHPR3 {
167 &self.shpr3
168 }
169 #[doc = "0xed24 - Use the System Handler Control and State Register to determine or clear the pending status of SVCall."]
170 #[inline(always)]
171 pub const fn shcsr(&self) -> &SHCSR {
172 &self.shcsr
173 }
174 #[doc = "0xed90 - Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports."]
175 #[inline(always)]
176 pub const fn mpu_type(&self) -> &MPU_TYPE {
177 &self.mpu_type
178 }
179 #[doc = "0xed94 - Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs."]
180 #[inline(always)]
181 pub const fn mpu_ctrl(&self) -> &MPU_CTRL {
182 &self.mpu_ctrl
183 }
184 #[doc = "0xed98 - Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR."]
185 #[inline(always)]
186 pub const fn mpu_rnr(&self) -> &MPU_RNR {
187 &self.mpu_rnr
188 }
189 #[doc = "0xed9c - Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated."]
190 #[inline(always)]
191 pub const fn mpu_rbar(&self) -> &MPU_RBAR {
192 &self.mpu_rbar
193 }
194 #[doc = "0xeda0 - Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region."]
195 #[inline(always)]
196 pub const fn mpu_rasr(&self) -> &MPU_RASR {
197 &self.mpu_rasr
198 }
199}
200#[doc = "SYST_CSR (rw) register accessor: Use the SysTick Control and Status Register to enable the SysTick features.
201
202You can [`read`](crate::generic::Reg::read) this register and get [`syst_csr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
203
204For information about available fields see [`mod@syst_csr`]
205module"]
206pub type SYST_CSR = crate::Reg<syst_csr::SYST_CSR_SPEC>;
207#[doc = "Use the SysTick Control and Status Register to enable the SysTick features."]
208pub mod syst_csr;
209#[doc = "SYST_RVR (rw) register accessor: Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.
210 To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.
211
212You can [`read`](crate::generic::Reg::read) this register and get [`syst_rvr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_rvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214For information about available fields see [`mod@syst_rvr`]
215module"]
216pub type SYST_RVR = crate::Reg<syst_rvr::SYST_RVR_SPEC>;
217#[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.
218 To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99."]
219pub mod syst_rvr;
220#[doc = "SYST_CVR (rw) register accessor: Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.
221
222You can [`read`](crate::generic::Reg::read) this register and get [`syst_cvr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
223
224For information about available fields see [`mod@syst_cvr`]
225module"]
226pub type SYST_CVR = crate::Reg<syst_cvr::SYST_CVR_SPEC>;
227#[doc = "Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN."]
228pub mod syst_cvr;
229#[doc = "SYST_CALIB (r) register accessor: Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.
230
231You can [`read`](crate::generic::Reg::read) this register and get [`syst_calib::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
232
233For information about available fields see [`mod@syst_calib`]
234module"]
235pub type SYST_CALIB = crate::Reg<syst_calib::SYST_CALIB_SPEC>;
236#[doc = "Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply."]
237pub mod syst_calib;
238#[doc = "NVIC_ISER (rw) register accessor: Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.
239 If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
240
241You can [`read`](crate::generic::Reg::read) this register and get [`nvic_iser::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_iser::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
242
243For information about available fields see [`mod@nvic_iser`]
244module"]
245pub type NVIC_ISER = crate::Reg<nvic_iser::NVIC_ISER_SPEC>;
246#[doc = "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.
247 If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority."]
248pub mod nvic_iser;
249#[doc = "NVIC_ICER (rw) register accessor: Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.
250
251You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icer::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
252
253For information about available fields see [`mod@nvic_icer`]
254module"]
255pub type NVIC_ICER = crate::Reg<nvic_icer::NVIC_ICER_SPEC>;
256#[doc = "Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled."]
257pub mod nvic_icer;
258#[doc = "NVIC_ISPR (rw) register accessor: The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.
259
260You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ispr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ispr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
261
262For information about available fields see [`mod@nvic_ispr`]
263module"]
264pub type NVIC_ISPR = crate::Reg<nvic_ispr::NVIC_ISPR_SPEC>;
265#[doc = "The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending."]
266pub mod nvic_ispr;
267#[doc = "NVIC_ICPR (rw) register accessor: Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.
268
269You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
270
271For information about available fields see [`mod@nvic_icpr`]
272module"]
273pub type NVIC_ICPR = crate::Reg<nvic_icpr::NVIC_ICPR_SPEC>;
274#[doc = "Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending."]
275pub mod nvic_icpr;
276#[doc = "NVIC_IPR0 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
277 Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
278 These registers are only word-accessible
279
280You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
281
282For information about available fields see [`mod@nvic_ipr0`]
283module"]
284pub type NVIC_IPR0 = crate::Reg<nvic_ipr0::NVIC_IPR0_SPEC>;
285#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
286 Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
287 These registers are only word-accessible"]
288pub mod nvic_ipr0;
289#[doc = "NVIC_IPR1 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
290
291You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
292
293For information about available fields see [`mod@nvic_ipr1`]
294module"]
295pub type NVIC_IPR1 = crate::Reg<nvic_ipr1::NVIC_IPR1_SPEC>;
296#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
297pub mod nvic_ipr1;
298#[doc = "NVIC_IPR2 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
299
300You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
301
302For information about available fields see [`mod@nvic_ipr2`]
303module"]
304pub type NVIC_IPR2 = crate::Reg<nvic_ipr2::NVIC_IPR2_SPEC>;
305#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
306pub mod nvic_ipr2;
307#[doc = "NVIC_IPR3 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
308
309You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
310
311For information about available fields see [`mod@nvic_ipr3`]
312module"]
313pub type NVIC_IPR3 = crate::Reg<nvic_ipr3::NVIC_IPR3_SPEC>;
314#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
315pub mod nvic_ipr3;
316#[doc = "NVIC_IPR4 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
317
318You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
319
320For information about available fields see [`mod@nvic_ipr4`]
321module"]
322pub type NVIC_IPR4 = crate::Reg<nvic_ipr4::NVIC_IPR4_SPEC>;
323#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
324pub mod nvic_ipr4;
325#[doc = "NVIC_IPR5 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
326
327You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
328
329For information about available fields see [`mod@nvic_ipr5`]
330module"]
331pub type NVIC_IPR5 = crate::Reg<nvic_ipr5::NVIC_IPR5_SPEC>;
332#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
333pub mod nvic_ipr5;
334#[doc = "NVIC_IPR6 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
335
336You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
337
338For information about available fields see [`mod@nvic_ipr6`]
339module"]
340pub type NVIC_IPR6 = crate::Reg<nvic_ipr6::NVIC_IPR6_SPEC>;
341#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
342pub mod nvic_ipr6;
343#[doc = "NVIC_IPR7 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
344
345You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
346
347For information about available fields see [`mod@nvic_ipr7`]
348module"]
349pub type NVIC_IPR7 = crate::Reg<nvic_ipr7::NVIC_IPR7_SPEC>;
350#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."]
351pub mod nvic_ipr7;
352#[doc = "CPUID (r) register accessor: Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.
353
354You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
355
356For information about available fields see [`mod@cpuid`]
357module"]
358pub type CPUID = crate::Reg<cpuid::CPUID_SPEC>;
359#[doc = "Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core."]
360pub mod cpuid;
361#[doc = "ICSR (rw) register accessor: Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.
362
363You can [`read`](crate::generic::Reg::read) this register and get [`icsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
364
365For information about available fields see [`mod@icsr`]
366module"]
367pub type ICSR = crate::Reg<icsr::ICSR_SPEC>;
368#[doc = "Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception."]
369pub mod icsr;
370#[doc = "VTOR (rw) register accessor: The VTOR holds the vector table offset address.
371
372You can [`read`](crate::generic::Reg::read) this register and get [`vtor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
373
374For information about available fields see [`mod@vtor`]
375module"]
376pub type VTOR = crate::Reg<vtor::VTOR_SPEC>;
377#[doc = "The VTOR holds the vector table offset address."]
378pub mod vtor;
379#[doc = "AIRCR (rw) register accessor: Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.
380
381You can [`read`](crate::generic::Reg::read) this register and get [`aircr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aircr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
382
383For information about available fields see [`mod@aircr`]
384module"]
385pub type AIRCR = crate::Reg<aircr::AIRCR_SPEC>;
386#[doc = "Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset."]
387pub mod aircr;
388#[doc = "SCR (rw) register accessor: System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.
389
390You can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
391
392For information about available fields see [`mod@scr`]
393module"]
394pub type SCR = crate::Reg<scr::SCR_SPEC>;
395#[doc = "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states."]
396pub mod scr;
397#[doc = "CCR (r) register accessor: The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.
398
399You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
400
401For information about available fields see [`mod@ccr`]
402module"]
403pub type CCR = crate::Reg<ccr::CCR_SPEC>;
404#[doc = "The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault."]
405pub mod ccr;
406#[doc = "SHPR2 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.
407
408You can [`read`](crate::generic::Reg::read) this register and get [`shpr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
409
410For information about available fields see [`mod@shpr2`]
411module"]
412pub type SHPR2 = crate::Reg<shpr2::SHPR2_SPEC>;
413#[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall."]
414pub mod shpr2;
415#[doc = "SHPR3 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.
416
417You can [`read`](crate::generic::Reg::read) this register and get [`shpr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
418
419For information about available fields see [`mod@shpr3`]
420module"]
421pub type SHPR3 = crate::Reg<shpr3::SHPR3_SPEC>;
422#[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick."]
423pub mod shpr3;
424#[doc = "SHCSR (rw) register accessor: Use the System Handler Control and State Register to determine or clear the pending status of SVCall.
425
426You can [`read`](crate::generic::Reg::read) this register and get [`shcsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shcsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
427
428For information about available fields see [`mod@shcsr`]
429module"]
430pub type SHCSR = crate::Reg<shcsr::SHCSR_SPEC>;
431#[doc = "Use the System Handler Control and State Register to determine or clear the pending status of SVCall."]
432pub mod shcsr;
433#[doc = "MPU_TYPE (r) register accessor: Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.
434
435You can [`read`](crate::generic::Reg::read) this register and get [`mpu_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
436
437For information about available fields see [`mod@mpu_type`]
438module"]
439pub type MPU_TYPE = crate::Reg<mpu_type::MPU_TYPE_SPEC>;
440#[doc = "Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports."]
441pub mod mpu_type;
442#[doc = "MPU_CTRL (rw) register accessor: Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.
443
444You can [`read`](crate::generic::Reg::read) this register and get [`mpu_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
445
446For information about available fields see [`mod@mpu_ctrl`]
447module"]
448pub type MPU_CTRL = crate::Reg<mpu_ctrl::MPU_CTRL_SPEC>;
449#[doc = "Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs."]
450pub mod mpu_ctrl;
451#[doc = "MPU_RNR (rw) register accessor: Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.
452
453You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rnr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rnr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
454
455For information about available fields see [`mod@mpu_rnr`]
456module"]
457pub type MPU_RNR = crate::Reg<mpu_rnr::MPU_RNR_SPEC>;
458#[doc = "Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR."]
459pub mod mpu_rnr;
460#[doc = "MPU_RBAR (rw) register accessor: Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.
461
462You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rbar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rbar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
463
464For information about available fields see [`mod@mpu_rbar`]
465module"]
466pub type MPU_RBAR = crate::Reg<mpu_rbar::MPU_RBAR_SPEC>;
467#[doc = "Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated."]
468pub mod mpu_rbar;
469#[doc = "MPU_RASR (rw) register accessor: Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.
470
471You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rasr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rasr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
472
473For information about available fields see [`mod@mpu_rasr`]
474module"]
475pub type MPU_RASR = crate::Reg<mpu_rasr::MPU_RASR_SPEC>;
476#[doc = "Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region."]
477pub mod mpu_rasr;