rp2040_pac/clocks/
enabled1.rs

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1#[doc = "Register `ENABLED1` reader"]
2pub type R = crate::R<ENABLED1_SPEC>;
3#[doc = "Field `clk_sys_sram4` reader - "]
4pub type CLK_SYS_SRAM4_R = crate::BitReader;
5#[doc = "Field `clk_sys_sram5` reader - "]
6pub type CLK_SYS_SRAM5_R = crate::BitReader;
7#[doc = "Field `clk_sys_syscfg` reader - "]
8pub type CLK_SYS_SYSCFG_R = crate::BitReader;
9#[doc = "Field `clk_sys_sysinfo` reader - "]
10pub type CLK_SYS_SYSINFO_R = crate::BitReader;
11#[doc = "Field `clk_sys_tbman` reader - "]
12pub type CLK_SYS_TBMAN_R = crate::BitReader;
13#[doc = "Field `clk_sys_timer` reader - "]
14pub type CLK_SYS_TIMER_R = crate::BitReader;
15#[doc = "Field `clk_peri_uart0` reader - "]
16pub type CLK_PERI_UART0_R = crate::BitReader;
17#[doc = "Field `clk_sys_uart0` reader - "]
18pub type CLK_SYS_UART0_R = crate::BitReader;
19#[doc = "Field `clk_peri_uart1` reader - "]
20pub type CLK_PERI_UART1_R = crate::BitReader;
21#[doc = "Field `clk_sys_uart1` reader - "]
22pub type CLK_SYS_UART1_R = crate::BitReader;
23#[doc = "Field `clk_sys_usbctrl` reader - "]
24pub type CLK_SYS_USBCTRL_R = crate::BitReader;
25#[doc = "Field `clk_usb_usbctrl` reader - "]
26pub type CLK_USB_USBCTRL_R = crate::BitReader;
27#[doc = "Field `clk_sys_watchdog` reader - "]
28pub type CLK_SYS_WATCHDOG_R = crate::BitReader;
29#[doc = "Field `clk_sys_xip` reader - "]
30pub type CLK_SYS_XIP_R = crate::BitReader;
31#[doc = "Field `clk_sys_xosc` reader - "]
32pub type CLK_SYS_XOSC_R = crate::BitReader;
33impl R {
34    #[doc = "Bit 0"]
35    #[inline(always)]
36    pub fn clk_sys_sram4(&self) -> CLK_SYS_SRAM4_R {
37        CLK_SYS_SRAM4_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 1"]
40    #[inline(always)]
41    pub fn clk_sys_sram5(&self) -> CLK_SYS_SRAM5_R {
42        CLK_SYS_SRAM5_R::new(((self.bits >> 1) & 1) != 0)
43    }
44    #[doc = "Bit 2"]
45    #[inline(always)]
46    pub fn clk_sys_syscfg(&self) -> CLK_SYS_SYSCFG_R {
47        CLK_SYS_SYSCFG_R::new(((self.bits >> 2) & 1) != 0)
48    }
49    #[doc = "Bit 3"]
50    #[inline(always)]
51    pub fn clk_sys_sysinfo(&self) -> CLK_SYS_SYSINFO_R {
52        CLK_SYS_SYSINFO_R::new(((self.bits >> 3) & 1) != 0)
53    }
54    #[doc = "Bit 4"]
55    #[inline(always)]
56    pub fn clk_sys_tbman(&self) -> CLK_SYS_TBMAN_R {
57        CLK_SYS_TBMAN_R::new(((self.bits >> 4) & 1) != 0)
58    }
59    #[doc = "Bit 5"]
60    #[inline(always)]
61    pub fn clk_sys_timer(&self) -> CLK_SYS_TIMER_R {
62        CLK_SYS_TIMER_R::new(((self.bits >> 5) & 1) != 0)
63    }
64    #[doc = "Bit 6"]
65    #[inline(always)]
66    pub fn clk_peri_uart0(&self) -> CLK_PERI_UART0_R {
67        CLK_PERI_UART0_R::new(((self.bits >> 6) & 1) != 0)
68    }
69    #[doc = "Bit 7"]
70    #[inline(always)]
71    pub fn clk_sys_uart0(&self) -> CLK_SYS_UART0_R {
72        CLK_SYS_UART0_R::new(((self.bits >> 7) & 1) != 0)
73    }
74    #[doc = "Bit 8"]
75    #[inline(always)]
76    pub fn clk_peri_uart1(&self) -> CLK_PERI_UART1_R {
77        CLK_PERI_UART1_R::new(((self.bits >> 8) & 1) != 0)
78    }
79    #[doc = "Bit 9"]
80    #[inline(always)]
81    pub fn clk_sys_uart1(&self) -> CLK_SYS_UART1_R {
82        CLK_SYS_UART1_R::new(((self.bits >> 9) & 1) != 0)
83    }
84    #[doc = "Bit 10"]
85    #[inline(always)]
86    pub fn clk_sys_usbctrl(&self) -> CLK_SYS_USBCTRL_R {
87        CLK_SYS_USBCTRL_R::new(((self.bits >> 10) & 1) != 0)
88    }
89    #[doc = "Bit 11"]
90    #[inline(always)]
91    pub fn clk_usb_usbctrl(&self) -> CLK_USB_USBCTRL_R {
92        CLK_USB_USBCTRL_R::new(((self.bits >> 11) & 1) != 0)
93    }
94    #[doc = "Bit 12"]
95    #[inline(always)]
96    pub fn clk_sys_watchdog(&self) -> CLK_SYS_WATCHDOG_R {
97        CLK_SYS_WATCHDOG_R::new(((self.bits >> 12) & 1) != 0)
98    }
99    #[doc = "Bit 13"]
100    #[inline(always)]
101    pub fn clk_sys_xip(&self) -> CLK_SYS_XIP_R {
102        CLK_SYS_XIP_R::new(((self.bits >> 13) & 1) != 0)
103    }
104    #[doc = "Bit 14"]
105    #[inline(always)]
106    pub fn clk_sys_xosc(&self) -> CLK_SYS_XOSC_R {
107        CLK_SYS_XOSC_R::new(((self.bits >> 14) & 1) != 0)
108    }
109}
110#[doc = "indicates the state of the clock enable  
111
112You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
113pub struct ENABLED1_SPEC;
114impl crate::RegisterSpec for ENABLED1_SPEC {
115    type Ux = u32;
116}
117#[doc = "`read()` method returns [`enabled1::R`](R) reader structure"]
118impl crate::Readable for ENABLED1_SPEC {}
119#[doc = "`reset()` method sets ENABLED1 to value 0"]
120impl crate::Resettable for ENABLED1_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
rp2040_pac/clocks/enabled1.rs

rp2040_pac/clocks/
enabled1.rs
