nrf52840_pac/nvmc/
icachecnf.rs
1#[doc = "Register `ICACHECNF` reader"]
2pub struct R(crate::R<ICACHECNF_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ICACHECNF_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ICACHECNF_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ICACHECNF_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `ICACHECNF` writer"]
17pub struct W(crate::W<ICACHECNF_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ICACHECNF_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ICACHECNF_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ICACHECNF_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CACHEEN` reader - Cache enable"]
38pub type CACHEEN_R = crate::BitReader<CACHEEN_A>;
39#[doc = "Cache enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41pub enum CACHEEN_A {
42 #[doc = "0: Disable cache. Invalidates all cache entries."]
43 DISABLED = 0,
44 #[doc = "1: Enable cache"]
45 ENABLED = 1,
46}
47impl From<CACHEEN_A> for bool {
48 #[inline(always)]
49 fn from(variant: CACHEEN_A) -> Self {
50 variant as u8 != 0
51 }
52}
53impl CACHEEN_R {
54 #[doc = "Get enumerated values variant"]
55 #[inline(always)]
56 pub fn variant(&self) -> CACHEEN_A {
57 match self.bits {
58 false => CACHEEN_A::DISABLED,
59 true => CACHEEN_A::ENABLED,
60 }
61 }
62 #[doc = "Checks if the value of the field is `DISABLED`"]
63 #[inline(always)]
64 pub fn is_disabled(&self) -> bool {
65 *self == CACHEEN_A::DISABLED
66 }
67 #[doc = "Checks if the value of the field is `ENABLED`"]
68 #[inline(always)]
69 pub fn is_enabled(&self) -> bool {
70 *self == CACHEEN_A::ENABLED
71 }
72}
73#[doc = "Field `CACHEEN` writer - Cache enable"]
74pub type CACHEEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICACHECNF_SPEC, CACHEEN_A, O>;
75impl<'a, const O: u8> CACHEEN_W<'a, O> {
76 #[doc = "Disable cache. Invalidates all cache entries."]
77 #[inline(always)]
78 pub fn disabled(self) -> &'a mut W {
79 self.variant(CACHEEN_A::DISABLED)
80 }
81 #[doc = "Enable cache"]
82 #[inline(always)]
83 pub fn enabled(self) -> &'a mut W {
84 self.variant(CACHEEN_A::ENABLED)
85 }
86}
87#[doc = "Field `CACHEPROFEN` reader - Cache profiling enable"]
88pub type CACHEPROFEN_R = crate::BitReader<CACHEPROFEN_A>;
89#[doc = "Cache profiling enable\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq)]
91pub enum CACHEPROFEN_A {
92 #[doc = "0: Disable cache profiling"]
93 DISABLED = 0,
94 #[doc = "1: Enable cache profiling"]
95 ENABLED = 1,
96}
97impl From<CACHEPROFEN_A> for bool {
98 #[inline(always)]
99 fn from(variant: CACHEPROFEN_A) -> Self {
100 variant as u8 != 0
101 }
102}
103impl CACHEPROFEN_R {
104 #[doc = "Get enumerated values variant"]
105 #[inline(always)]
106 pub fn variant(&self) -> CACHEPROFEN_A {
107 match self.bits {
108 false => CACHEPROFEN_A::DISABLED,
109 true => CACHEPROFEN_A::ENABLED,
110 }
111 }
112 #[doc = "Checks if the value of the field is `DISABLED`"]
113 #[inline(always)]
114 pub fn is_disabled(&self) -> bool {
115 *self == CACHEPROFEN_A::DISABLED
116 }
117 #[doc = "Checks if the value of the field is `ENABLED`"]
118 #[inline(always)]
119 pub fn is_enabled(&self) -> bool {
120 *self == CACHEPROFEN_A::ENABLED
121 }
122}
123#[doc = "Field `CACHEPROFEN` writer - Cache profiling enable"]
124pub type CACHEPROFEN_W<'a, const O: u8> =
125 crate::BitWriter<'a, u32, ICACHECNF_SPEC, CACHEPROFEN_A, O>;
126impl<'a, const O: u8> CACHEPROFEN_W<'a, O> {
127 #[doc = "Disable cache profiling"]
128 #[inline(always)]
129 pub fn disabled(self) -> &'a mut W {
130 self.variant(CACHEPROFEN_A::DISABLED)
131 }
132 #[doc = "Enable cache profiling"]
133 #[inline(always)]
134 pub fn enabled(self) -> &'a mut W {
135 self.variant(CACHEPROFEN_A::ENABLED)
136 }
137}
138impl R {
139 #[doc = "Bit 0 - Cache enable"]
140 #[inline(always)]
141 pub fn cacheen(&self) -> CACHEEN_R {
142 CACHEEN_R::new((self.bits & 1) != 0)
143 }
144 #[doc = "Bit 8 - Cache profiling enable"]
145 #[inline(always)]
146 pub fn cacheprofen(&self) -> CACHEPROFEN_R {
147 CACHEPROFEN_R::new(((self.bits >> 8) & 1) != 0)
148 }
149}
150impl W {
151 #[doc = "Bit 0 - Cache enable"]
152 #[inline(always)]
153 pub fn cacheen(&mut self) -> CACHEEN_W<0> {
154 CACHEEN_W::new(self)
155 }
156 #[doc = "Bit 8 - Cache profiling enable"]
157 #[inline(always)]
158 pub fn cacheprofen(&mut self) -> CACHEPROFEN_W<8> {
159 CACHEPROFEN_W::new(self)
160 }
161 #[doc = "Writes raw bits to the register."]
162 #[inline(always)]
163 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
164 self.0.bits(bits);
165 self
166 }
167}
168#[doc = "I-code cache configuration register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icachecnf](index.html) module"]
169pub struct ICACHECNF_SPEC;
170impl crate::RegisterSpec for ICACHECNF_SPEC {
171 type Ux = u32;
172}
173#[doc = "`read()` method returns [icachecnf::R](R) reader structure"]
174impl crate::Readable for ICACHECNF_SPEC {
175 type Reader = R;
176}
177#[doc = "`write(|w| ..)` method takes [icachecnf::W](W) writer structure"]
178impl crate::Writable for ICACHECNF_SPEC {
179 type Writer = W;
180}
181#[doc = "`reset()` method sets ICACHECNF to value 0"]
182impl crate::Resettable for ICACHECNF_SPEC {
183 #[inline(always)]
184 fn reset_value() -> Self::Ux {
185 0
186 }
187}