1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 clk_gpout0_ctrl: CLK_GPOUT0_CTRL,
5 clk_gpout0_div: CLK_GPOUT0_DIV,
6 clk_gpout0_selected: CLK_GPOUT0_SELECTED,
7 clk_gpout1_ctrl: CLK_GPOUT1_CTRL,
8 clk_gpout1_div: CLK_GPOUT1_DIV,
9 clk_gpout1_selected: CLK_GPOUT1_SELECTED,
10 clk_gpout2_ctrl: CLK_GPOUT2_CTRL,
11 clk_gpout2_div: CLK_GPOUT2_DIV,
12 clk_gpout2_selected: CLK_GPOUT2_SELECTED,
13 clk_gpout3_ctrl: CLK_GPOUT3_CTRL,
14 clk_gpout3_div: CLK_GPOUT3_DIV,
15 clk_gpout3_selected: CLK_GPOUT3_SELECTED,
16 clk_ref_ctrl: CLK_REF_CTRL,
17 clk_ref_div: CLK_REF_DIV,
18 clk_ref_selected: CLK_REF_SELECTED,
19 clk_sys_ctrl: CLK_SYS_CTRL,
20 clk_sys_div: CLK_SYS_DIV,
21 clk_sys_selected: CLK_SYS_SELECTED,
22 clk_peri_ctrl: CLK_PERI_CTRL,
23 _reserved19: [u8; 0x04],
24 clk_peri_selected: CLK_PERI_SELECTED,
25 clk_usb_ctrl: CLK_USB_CTRL,
26 clk_usb_div: CLK_USB_DIV,
27 clk_usb_selected: CLK_USB_SELECTED,
28 clk_adc_ctrl: CLK_ADC_CTRL,
29 clk_adc_div: CLK_ADC_DIV,
30 clk_adc_selected: CLK_ADC_SELECTED,
31 clk_rtc_ctrl: CLK_RTC_CTRL,
32 clk_rtc_div: CLK_RTC_DIV,
33 clk_rtc_selected: CLK_RTC_SELECTED,
34 clk_sys_resus_ctrl: CLK_SYS_RESUS_CTRL,
35 clk_sys_resus_status: CLK_SYS_RESUS_STATUS,
36 fc0_ref_khz: FC0_REF_KHZ,
37 fc0_min_khz: FC0_MIN_KHZ,
38 fc0_max_khz: FC0_MAX_KHZ,
39 fc0_delay: FC0_DELAY,
40 fc0_interval: FC0_INTERVAL,
41 fc0_src: FC0_SRC,
42 fc0_status: FC0_STATUS,
43 fc0_result: FC0_RESULT,
44 wake_en0: WAKE_EN0,
45 wake_en1: WAKE_EN1,
46 sleep_en0: SLEEP_EN0,
47 sleep_en1: SLEEP_EN1,
48 enabled0: ENABLED0,
49 enabled1: ENABLED1,
50 intr: INTR,
51 inte: INTE,
52 intf: INTF,
53 ints: INTS,
54}
55impl RegisterBlock {
56 #[doc = "0x00 - Clock control, can be changed on-the-fly (except for auxsrc)"]
57 #[inline(always)]
58 pub const fn clk_gpout0_ctrl(&self) -> &CLK_GPOUT0_CTRL {
59 &self.clk_gpout0_ctrl
60 }
61 #[doc = "0x04 - Clock divisor, can be changed on-the-fly"]
62 #[inline(always)]
63 pub const fn clk_gpout0_div(&self) -> &CLK_GPOUT0_DIV {
64 &self.clk_gpout0_div
65 }
66 #[doc = "0x08 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
67 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
68 #[inline(always)]
69 pub const fn clk_gpout0_selected(&self) -> &CLK_GPOUT0_SELECTED {
70 &self.clk_gpout0_selected
71 }
72 #[doc = "0x0c - Clock control, can be changed on-the-fly (except for auxsrc)"]
73 #[inline(always)]
74 pub const fn clk_gpout1_ctrl(&self) -> &CLK_GPOUT1_CTRL {
75 &self.clk_gpout1_ctrl
76 }
77 #[doc = "0x10 - Clock divisor, can be changed on-the-fly"]
78 #[inline(always)]
79 pub const fn clk_gpout1_div(&self) -> &CLK_GPOUT1_DIV {
80 &self.clk_gpout1_div
81 }
82 #[doc = "0x14 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
83 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
84 #[inline(always)]
85 pub const fn clk_gpout1_selected(&self) -> &CLK_GPOUT1_SELECTED {
86 &self.clk_gpout1_selected
87 }
88 #[doc = "0x18 - Clock control, can be changed on-the-fly (except for auxsrc)"]
89 #[inline(always)]
90 pub const fn clk_gpout2_ctrl(&self) -> &CLK_GPOUT2_CTRL {
91 &self.clk_gpout2_ctrl
92 }
93 #[doc = "0x1c - Clock divisor, can be changed on-the-fly"]
94 #[inline(always)]
95 pub const fn clk_gpout2_div(&self) -> &CLK_GPOUT2_DIV {
96 &self.clk_gpout2_div
97 }
98 #[doc = "0x20 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
99 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
100 #[inline(always)]
101 pub const fn clk_gpout2_selected(&self) -> &CLK_GPOUT2_SELECTED {
102 &self.clk_gpout2_selected
103 }
104 #[doc = "0x24 - Clock control, can be changed on-the-fly (except for auxsrc)"]
105 #[inline(always)]
106 pub const fn clk_gpout3_ctrl(&self) -> &CLK_GPOUT3_CTRL {
107 &self.clk_gpout3_ctrl
108 }
109 #[doc = "0x28 - Clock divisor, can be changed on-the-fly"]
110 #[inline(always)]
111 pub const fn clk_gpout3_div(&self) -> &CLK_GPOUT3_DIV {
112 &self.clk_gpout3_div
113 }
114 #[doc = "0x2c - Indicates which SRC is currently selected by the glitchless mux (one-hot).
115 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
116 #[inline(always)]
117 pub const fn clk_gpout3_selected(&self) -> &CLK_GPOUT3_SELECTED {
118 &self.clk_gpout3_selected
119 }
120 #[doc = "0x30 - Clock control, can be changed on-the-fly (except for auxsrc)"]
121 #[inline(always)]
122 pub const fn clk_ref_ctrl(&self) -> &CLK_REF_CTRL {
123 &self.clk_ref_ctrl
124 }
125 #[doc = "0x34 - Clock divisor, can be changed on-the-fly"]
126 #[inline(always)]
127 pub const fn clk_ref_div(&self) -> &CLK_REF_DIV {
128 &self.clk_ref_div
129 }
130 #[doc = "0x38 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
131 The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
132 #[inline(always)]
133 pub const fn clk_ref_selected(&self) -> &CLK_REF_SELECTED {
134 &self.clk_ref_selected
135 }
136 #[doc = "0x3c - Clock control, can be changed on-the-fly (except for auxsrc)"]
137 #[inline(always)]
138 pub const fn clk_sys_ctrl(&self) -> &CLK_SYS_CTRL {
139 &self.clk_sys_ctrl
140 }
141 #[doc = "0x40 - Clock divisor, can be changed on-the-fly"]
142 #[inline(always)]
143 pub const fn clk_sys_div(&self) -> &CLK_SYS_DIV {
144 &self.clk_sys_div
145 }
146 #[doc = "0x44 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
147 The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
148 #[inline(always)]
149 pub const fn clk_sys_selected(&self) -> &CLK_SYS_SELECTED {
150 &self.clk_sys_selected
151 }
152 #[doc = "0x48 - Clock control, can be changed on-the-fly (except for auxsrc)"]
153 #[inline(always)]
154 pub const fn clk_peri_ctrl(&self) -> &CLK_PERI_CTRL {
155 &self.clk_peri_ctrl
156 }
157 #[doc = "0x50 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
158 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
159 #[inline(always)]
160 pub const fn clk_peri_selected(&self) -> &CLK_PERI_SELECTED {
161 &self.clk_peri_selected
162 }
163 #[doc = "0x54 - Clock control, can be changed on-the-fly (except for auxsrc)"]
164 #[inline(always)]
165 pub const fn clk_usb_ctrl(&self) -> &CLK_USB_CTRL {
166 &self.clk_usb_ctrl
167 }
168 #[doc = "0x58 - Clock divisor, can be changed on-the-fly"]
169 #[inline(always)]
170 pub const fn clk_usb_div(&self) -> &CLK_USB_DIV {
171 &self.clk_usb_div
172 }
173 #[doc = "0x5c - Indicates which SRC is currently selected by the glitchless mux (one-hot).
174 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
175 #[inline(always)]
176 pub const fn clk_usb_selected(&self) -> &CLK_USB_SELECTED {
177 &self.clk_usb_selected
178 }
179 #[doc = "0x60 - Clock control, can be changed on-the-fly (except for auxsrc)"]
180 #[inline(always)]
181 pub const fn clk_adc_ctrl(&self) -> &CLK_ADC_CTRL {
182 &self.clk_adc_ctrl
183 }
184 #[doc = "0x64 - Clock divisor, can be changed on-the-fly"]
185 #[inline(always)]
186 pub const fn clk_adc_div(&self) -> &CLK_ADC_DIV {
187 &self.clk_adc_div
188 }
189 #[doc = "0x68 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
190 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
191 #[inline(always)]
192 pub const fn clk_adc_selected(&self) -> &CLK_ADC_SELECTED {
193 &self.clk_adc_selected
194 }
195 #[doc = "0x6c - Clock control, can be changed on-the-fly (except for auxsrc)"]
196 #[inline(always)]
197 pub const fn clk_rtc_ctrl(&self) -> &CLK_RTC_CTRL {
198 &self.clk_rtc_ctrl
199 }
200 #[doc = "0x70 - Clock divisor, can be changed on-the-fly"]
201 #[inline(always)]
202 pub const fn clk_rtc_div(&self) -> &CLK_RTC_DIV {
203 &self.clk_rtc_div
204 }
205 #[doc = "0x74 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
206 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
207 #[inline(always)]
208 pub const fn clk_rtc_selected(&self) -> &CLK_RTC_SELECTED {
209 &self.clk_rtc_selected
210 }
211 #[doc = "0x78 - "]
212 #[inline(always)]
213 pub const fn clk_sys_resus_ctrl(&self) -> &CLK_SYS_RESUS_CTRL {
214 &self.clk_sys_resus_ctrl
215 }
216 #[doc = "0x7c - "]
217 #[inline(always)]
218 pub const fn clk_sys_resus_status(&self) -> &CLK_SYS_RESUS_STATUS {
219 &self.clk_sys_resus_status
220 }
221 #[doc = "0x80 - Reference clock frequency in kHz"]
222 #[inline(always)]
223 pub const fn fc0_ref_khz(&self) -> &FC0_REF_KHZ {
224 &self.fc0_ref_khz
225 }
226 #[doc = "0x84 - Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"]
227 #[inline(always)]
228 pub const fn fc0_min_khz(&self) -> &FC0_MIN_KHZ {
229 &self.fc0_min_khz
230 }
231 #[doc = "0x88 - Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"]
232 #[inline(always)]
233 pub const fn fc0_max_khz(&self) -> &FC0_MAX_KHZ {
234 &self.fc0_max_khz
235 }
236 #[doc = "0x8c - Delays the start of frequency counting to allow the mux to settle
237 Delay is measured in multiples of the reference clock period"]
238 #[inline(always)]
239 pub const fn fc0_delay(&self) -> &FC0_DELAY {
240 &self.fc0_delay
241 }
242 #[doc = "0x90 - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval
243 The default gives a test interval of 250us"]
244 #[inline(always)]
245 pub const fn fc0_interval(&self) -> &FC0_INTERVAL {
246 &self.fc0_interval
247 }
248 #[doc = "0x94 - Clock sent to frequency counter, set to 0 when not required
249 Writing to this register initiates the frequency count"]
250 #[inline(always)]
251 pub const fn fc0_src(&self) -> &FC0_SRC {
252 &self.fc0_src
253 }
254 #[doc = "0x98 - Frequency counter status"]
255 #[inline(always)]
256 pub const fn fc0_status(&self) -> &FC0_STATUS {
257 &self.fc0_status
258 }
259 #[doc = "0x9c - Result of frequency measurement, only valid when status_done=1"]
260 #[inline(always)]
261 pub const fn fc0_result(&self) -> &FC0_RESULT {
262 &self.fc0_result
263 }
264 #[doc = "0xa0 - enable clock in wake mode"]
265 #[inline(always)]
266 pub const fn wake_en0(&self) -> &WAKE_EN0 {
267 &self.wake_en0
268 }
269 #[doc = "0xa4 - enable clock in wake mode"]
270 #[inline(always)]
271 pub const fn wake_en1(&self) -> &WAKE_EN1 {
272 &self.wake_en1
273 }
274 #[doc = "0xa8 - enable clock in sleep mode"]
275 #[inline(always)]
276 pub const fn sleep_en0(&self) -> &SLEEP_EN0 {
277 &self.sleep_en0
278 }
279 #[doc = "0xac - enable clock in sleep mode"]
280 #[inline(always)]
281 pub const fn sleep_en1(&self) -> &SLEEP_EN1 {
282 &self.sleep_en1
283 }
284 #[doc = "0xb0 - indicates the state of the clock enable"]
285 #[inline(always)]
286 pub const fn enabled0(&self) -> &ENABLED0 {
287 &self.enabled0
288 }
289 #[doc = "0xb4 - indicates the state of the clock enable"]
290 #[inline(always)]
291 pub const fn enabled1(&self) -> &ENABLED1 {
292 &self.enabled1
293 }
294 #[doc = "0xb8 - Raw Interrupts"]
295 #[inline(always)]
296 pub const fn intr(&self) -> &INTR {
297 &self.intr
298 }
299 #[doc = "0xbc - Interrupt Enable"]
300 #[inline(always)]
301 pub const fn inte(&self) -> &INTE {
302 &self.inte
303 }
304 #[doc = "0xc0 - Interrupt Force"]
305 #[inline(always)]
306 pub const fn intf(&self) -> &INTF {
307 &self.intf
308 }
309 #[doc = "0xc4 - Interrupt status after masking & forcing"]
310 #[inline(always)]
311 pub const fn ints(&self) -> &INTS {
312 &self.ints
313 }
314}
315#[doc = "CLK_GPOUT0_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
316
317You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
318
319For information about available fields see [`mod@clk_gpout0_ctrl`]
320module"]
321pub type CLK_GPOUT0_CTRL = crate::Reg<clk_gpout0_ctrl::CLK_GPOUT0_CTRL_SPEC>;
322#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
323pub mod clk_gpout0_ctrl;
324#[doc = "CLK_GPOUT0_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly
325
326You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
327
328For information about available fields see [`mod@clk_gpout0_div`]
329module"]
330pub type CLK_GPOUT0_DIV = crate::Reg<clk_gpout0_div::CLK_GPOUT0_DIV_SPEC>;
331#[doc = "Clock divisor, can be changed on-the-fly"]
332pub mod clk_gpout0_div;
333#[doc = "CLK_GPOUT0_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
334 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
335
336You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
337
338For information about available fields see [`mod@clk_gpout0_selected`]
339module"]
340pub type CLK_GPOUT0_SELECTED = crate::Reg<clk_gpout0_selected::CLK_GPOUT0_SELECTED_SPEC>;
341#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
342 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
343pub mod clk_gpout0_selected;
344#[doc = "CLK_GPOUT1_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
345
346You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
347
348For information about available fields see [`mod@clk_gpout1_ctrl`]
349module"]
350pub type CLK_GPOUT1_CTRL = crate::Reg<clk_gpout1_ctrl::CLK_GPOUT1_CTRL_SPEC>;
351#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
352pub mod clk_gpout1_ctrl;
353#[doc = "CLK_GPOUT1_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly
354
355You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
356
357For information about available fields see [`mod@clk_gpout1_div`]
358module"]
359pub type CLK_GPOUT1_DIV = crate::Reg<clk_gpout1_div::CLK_GPOUT1_DIV_SPEC>;
360#[doc = "Clock divisor, can be changed on-the-fly"]
361pub mod clk_gpout1_div;
362#[doc = "CLK_GPOUT1_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
363 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
364
365You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
366
367For information about available fields see [`mod@clk_gpout1_selected`]
368module"]
369pub type CLK_GPOUT1_SELECTED = crate::Reg<clk_gpout1_selected::CLK_GPOUT1_SELECTED_SPEC>;
370#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
371 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
372pub mod clk_gpout1_selected;
373#[doc = "CLK_GPOUT2_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
374
375You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
376
377For information about available fields see [`mod@clk_gpout2_ctrl`]
378module"]
379pub type CLK_GPOUT2_CTRL = crate::Reg<clk_gpout2_ctrl::CLK_GPOUT2_CTRL_SPEC>;
380#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
381pub mod clk_gpout2_ctrl;
382#[doc = "CLK_GPOUT2_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly
383
384You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
385
386For information about available fields see [`mod@clk_gpout2_div`]
387module"]
388pub type CLK_GPOUT2_DIV = crate::Reg<clk_gpout2_div::CLK_GPOUT2_DIV_SPEC>;
389#[doc = "Clock divisor, can be changed on-the-fly"]
390pub mod clk_gpout2_div;
391#[doc = "CLK_GPOUT2_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
392 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
393
394You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
395
396For information about available fields see [`mod@clk_gpout2_selected`]
397module"]
398pub type CLK_GPOUT2_SELECTED = crate::Reg<clk_gpout2_selected::CLK_GPOUT2_SELECTED_SPEC>;
399#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
400 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
401pub mod clk_gpout2_selected;
402#[doc = "CLK_GPOUT3_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
403
404You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
405
406For information about available fields see [`mod@clk_gpout3_ctrl`]
407module"]
408pub type CLK_GPOUT3_CTRL = crate::Reg<clk_gpout3_ctrl::CLK_GPOUT3_CTRL_SPEC>;
409#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
410pub mod clk_gpout3_ctrl;
411#[doc = "CLK_GPOUT3_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly
412
413You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
414
415For information about available fields see [`mod@clk_gpout3_div`]
416module"]
417pub type CLK_GPOUT3_DIV = crate::Reg<clk_gpout3_div::CLK_GPOUT3_DIV_SPEC>;
418#[doc = "Clock divisor, can be changed on-the-fly"]
419pub mod clk_gpout3_div;
420#[doc = "CLK_GPOUT3_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
421 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
422
423You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
424
425For information about available fields see [`mod@clk_gpout3_selected`]
426module"]
427pub type CLK_GPOUT3_SELECTED = crate::Reg<clk_gpout3_selected::CLK_GPOUT3_SELECTED_SPEC>;
428#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
429 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
430pub mod clk_gpout3_selected;
431#[doc = "CLK_REF_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
432
433You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
434
435For information about available fields see [`mod@clk_ref_ctrl`]
436module"]
437pub type CLK_REF_CTRL = crate::Reg<clk_ref_ctrl::CLK_REF_CTRL_SPEC>;
438#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
439pub mod clk_ref_ctrl;
440#[doc = "CLK_REF_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly
441
442You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
443
444For information about available fields see [`mod@clk_ref_div`]
445module"]
446pub type CLK_REF_DIV = crate::Reg<clk_ref_div::CLK_REF_DIV_SPEC>;
447#[doc = "Clock divisor, can be changed on-the-fly"]
448pub mod clk_ref_div;
449#[doc = "CLK_REF_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
450 The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
451
452You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
453
454For information about available fields see [`mod@clk_ref_selected`]
455module"]
456pub type CLK_REF_SELECTED = crate::Reg<clk_ref_selected::CLK_REF_SELECTED_SPEC>;
457#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
458 The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
459pub mod clk_ref_selected;
460#[doc = "CLK_SYS_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
461
462You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
463
464For information about available fields see [`mod@clk_sys_ctrl`]
465module"]
466pub type CLK_SYS_CTRL = crate::Reg<clk_sys_ctrl::CLK_SYS_CTRL_SPEC>;
467#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
468pub mod clk_sys_ctrl;
469#[doc = "CLK_SYS_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly
470
471You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
472
473For information about available fields see [`mod@clk_sys_div`]
474module"]
475pub type CLK_SYS_DIV = crate::Reg<clk_sys_div::CLK_SYS_DIV_SPEC>;
476#[doc = "Clock divisor, can be changed on-the-fly"]
477pub mod clk_sys_div;
478#[doc = "CLK_SYS_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
479 The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
480
481You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
482
483For information about available fields see [`mod@clk_sys_selected`]
484module"]
485pub type CLK_SYS_SELECTED = crate::Reg<clk_sys_selected::CLK_SYS_SELECTED_SPEC>;
486#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
487 The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."]
488pub mod clk_sys_selected;
489#[doc = "CLK_PERI_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
490
491You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
492
493For information about available fields see [`mod@clk_peri_ctrl`]
494module"]
495pub type CLK_PERI_CTRL = crate::Reg<clk_peri_ctrl::CLK_PERI_CTRL_SPEC>;
496#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
497pub mod clk_peri_ctrl;
498#[doc = "CLK_PERI_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
499 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
500
501You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
502
503For information about available fields see [`mod@clk_peri_selected`]
504module"]
505pub type CLK_PERI_SELECTED = crate::Reg<clk_peri_selected::CLK_PERI_SELECTED_SPEC>;
506#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
507 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
508pub mod clk_peri_selected;
509#[doc = "CLK_USB_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
510
511You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
512
513For information about available fields see [`mod@clk_usb_ctrl`]
514module"]
515pub type CLK_USB_CTRL = crate::Reg<clk_usb_ctrl::CLK_USB_CTRL_SPEC>;
516#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
517pub mod clk_usb_ctrl;
518#[doc = "CLK_USB_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly
519
520You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
521
522For information about available fields see [`mod@clk_usb_div`]
523module"]
524pub type CLK_USB_DIV = crate::Reg<clk_usb_div::CLK_USB_DIV_SPEC>;
525#[doc = "Clock divisor, can be changed on-the-fly"]
526pub mod clk_usb_div;
527#[doc = "CLK_USB_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
528 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
529
530You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
531
532For information about available fields see [`mod@clk_usb_selected`]
533module"]
534pub type CLK_USB_SELECTED = crate::Reg<clk_usb_selected::CLK_USB_SELECTED_SPEC>;
535#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
536 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
537pub mod clk_usb_selected;
538#[doc = "CLK_ADC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
539
540You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
541
542For information about available fields see [`mod@clk_adc_ctrl`]
543module"]
544pub type CLK_ADC_CTRL = crate::Reg<clk_adc_ctrl::CLK_ADC_CTRL_SPEC>;
545#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
546pub mod clk_adc_ctrl;
547#[doc = "CLK_ADC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly
548
549You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
550
551For information about available fields see [`mod@clk_adc_div`]
552module"]
553pub type CLK_ADC_DIV = crate::Reg<clk_adc_div::CLK_ADC_DIV_SPEC>;
554#[doc = "Clock divisor, can be changed on-the-fly"]
555pub mod clk_adc_div;
556#[doc = "CLK_ADC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
557 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
558
559You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
560
561For information about available fields see [`mod@clk_adc_selected`]
562module"]
563pub type CLK_ADC_SELECTED = crate::Reg<clk_adc_selected::CLK_ADC_SELECTED_SPEC>;
564#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
565 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
566pub mod clk_adc_selected;
567#[doc = "CLK_RTC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)
568
569You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
570
571For information about available fields see [`mod@clk_rtc_ctrl`]
572module"]
573pub type CLK_RTC_CTRL = crate::Reg<clk_rtc_ctrl::CLK_RTC_CTRL_SPEC>;
574#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"]
575pub mod clk_rtc_ctrl;
576#[doc = "CLK_RTC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly
577
578You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
579
580For information about available fields see [`mod@clk_rtc_div`]
581module"]
582pub type CLK_RTC_DIV = crate::Reg<clk_rtc_div::CLK_RTC_DIV_SPEC>;
583#[doc = "Clock divisor, can be changed on-the-fly"]
584pub mod clk_rtc_div;
585#[doc = "CLK_RTC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
586 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
587
588You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
589
590For information about available fields see [`mod@clk_rtc_selected`]
591module"]
592pub type CLK_RTC_SELECTED = crate::Reg<clk_rtc_selected::CLK_RTC_SELECTED_SPEC>;
593#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).
594 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."]
595pub mod clk_rtc_selected;
596#[doc = "CLK_SYS_RESUS_CTRL (rw) register accessor:
597
598You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
599
600For information about available fields see [`mod@clk_sys_resus_ctrl`]
601module"]
602pub type CLK_SYS_RESUS_CTRL = crate::Reg<clk_sys_resus_ctrl::CLK_SYS_RESUS_CTRL_SPEC>;
603#[doc = ""]
604pub mod clk_sys_resus_ctrl;
605#[doc = "CLK_SYS_RESUS_STATUS (r) register accessor:
606
607You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
608
609For information about available fields see [`mod@clk_sys_resus_status`]
610module"]
611pub type CLK_SYS_RESUS_STATUS = crate::Reg<clk_sys_resus_status::CLK_SYS_RESUS_STATUS_SPEC>;
612#[doc = ""]
613pub mod clk_sys_resus_status;
614#[doc = "FC0_REF_KHZ (rw) register accessor: Reference clock frequency in kHz
615
616You can [`read`](crate::generic::Reg::read) this register and get [`fc0_ref_khz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_ref_khz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
617
618For information about available fields see [`mod@fc0_ref_khz`]
619module"]
620pub type FC0_REF_KHZ = crate::Reg<fc0_ref_khz::FC0_REF_KHZ_SPEC>;
621#[doc = "Reference clock frequency in kHz"]
622pub mod fc0_ref_khz;
623#[doc = "FC0_MIN_KHZ (rw) register accessor: Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags
624
625You can [`read`](crate::generic::Reg::read) this register and get [`fc0_min_khz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_min_khz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
626
627For information about available fields see [`mod@fc0_min_khz`]
628module"]
629pub type FC0_MIN_KHZ = crate::Reg<fc0_min_khz::FC0_MIN_KHZ_SPEC>;
630#[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"]
631pub mod fc0_min_khz;
632#[doc = "FC0_MAX_KHZ (rw) register accessor: Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags
633
634You can [`read`](crate::generic::Reg::read) this register and get [`fc0_max_khz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_max_khz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
635
636For information about available fields see [`mod@fc0_max_khz`]
637module"]
638pub type FC0_MAX_KHZ = crate::Reg<fc0_max_khz::FC0_MAX_KHZ_SPEC>;
639#[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"]
640pub mod fc0_max_khz;
641#[doc = "FC0_DELAY (rw) register accessor: Delays the start of frequency counting to allow the mux to settle
642 Delay is measured in multiples of the reference clock period
643
644You can [`read`](crate::generic::Reg::read) this register and get [`fc0_delay::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_delay::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
645
646For information about available fields see [`mod@fc0_delay`]
647module"]
648pub type FC0_DELAY = crate::Reg<fc0_delay::FC0_DELAY_SPEC>;
649#[doc = "Delays the start of frequency counting to allow the mux to settle
650 Delay is measured in multiples of the reference clock period"]
651pub mod fc0_delay;
652#[doc = "FC0_INTERVAL (rw) register accessor: The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval
653 The default gives a test interval of 250us
654
655You can [`read`](crate::generic::Reg::read) this register and get [`fc0_interval::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_interval::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
656
657For information about available fields see [`mod@fc0_interval`]
658module"]
659pub type FC0_INTERVAL = crate::Reg<fc0_interval::FC0_INTERVAL_SPEC>;
660#[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval
661 The default gives a test interval of 250us"]
662pub mod fc0_interval;
663#[doc = "FC0_SRC (rw) register accessor: Clock sent to frequency counter, set to 0 when not required
664 Writing to this register initiates the frequency count
665
666You can [`read`](crate::generic::Reg::read) this register and get [`fc0_src::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
667
668For information about available fields see [`mod@fc0_src`]
669module"]
670pub type FC0_SRC = crate::Reg<fc0_src::FC0_SRC_SPEC>;
671#[doc = "Clock sent to frequency counter, set to 0 when not required
672 Writing to this register initiates the frequency count"]
673pub mod fc0_src;
674#[doc = "FC0_STATUS (r) register accessor: Frequency counter status
675
676You can [`read`](crate::generic::Reg::read) this register and get [`fc0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
677
678For information about available fields see [`mod@fc0_status`]
679module"]
680pub type FC0_STATUS = crate::Reg<fc0_status::FC0_STATUS_SPEC>;
681#[doc = "Frequency counter status"]
682pub mod fc0_status;
683#[doc = "FC0_RESULT (r) register accessor: Result of frequency measurement, only valid when status_done=1
684
685You can [`read`](crate::generic::Reg::read) this register and get [`fc0_result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
686
687For information about available fields see [`mod@fc0_result`]
688module"]
689pub type FC0_RESULT = crate::Reg<fc0_result::FC0_RESULT_SPEC>;
690#[doc = "Result of frequency measurement, only valid when status_done=1"]
691pub mod fc0_result;
692#[doc = "WAKE_EN0 (rw) register accessor: enable clock in wake mode
693
694You can [`read`](crate::generic::Reg::read) this register and get [`wake_en0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
695
696For information about available fields see [`mod@wake_en0`]
697module"]
698pub type WAKE_EN0 = crate::Reg<wake_en0::WAKE_EN0_SPEC>;
699#[doc = "enable clock in wake mode"]
700pub mod wake_en0;
701#[doc = "WAKE_EN1 (rw) register accessor: enable clock in wake mode
702
703You can [`read`](crate::generic::Reg::read) this register and get [`wake_en1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
704
705For information about available fields see [`mod@wake_en1`]
706module"]
707pub type WAKE_EN1 = crate::Reg<wake_en1::WAKE_EN1_SPEC>;
708#[doc = "enable clock in wake mode"]
709pub mod wake_en1;
710#[doc = "SLEEP_EN0 (rw) register accessor: enable clock in sleep mode
711
712You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
713
714For information about available fields see [`mod@sleep_en0`]
715module"]
716pub type SLEEP_EN0 = crate::Reg<sleep_en0::SLEEP_EN0_SPEC>;
717#[doc = "enable clock in sleep mode"]
718pub mod sleep_en0;
719#[doc = "SLEEP_EN1 (rw) register accessor: enable clock in sleep mode
720
721You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
722
723For information about available fields see [`mod@sleep_en1`]
724module"]
725pub type SLEEP_EN1 = crate::Reg<sleep_en1::SLEEP_EN1_SPEC>;
726#[doc = "enable clock in sleep mode"]
727pub mod sleep_en1;
728#[doc = "ENABLED0 (r) register accessor: indicates the state of the clock enable
729
730You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
731
732For information about available fields see [`mod@enabled0`]
733module"]
734pub type ENABLED0 = crate::Reg<enabled0::ENABLED0_SPEC>;
735#[doc = "indicates the state of the clock enable"]
736pub mod enabled0;
737#[doc = "ENABLED1 (r) register accessor: indicates the state of the clock enable
738
739You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
740
741For information about available fields see [`mod@enabled1`]
742module"]
743pub type ENABLED1 = crate::Reg<enabled1::ENABLED1_SPEC>;
744#[doc = "indicates the state of the clock enable"]
745pub mod enabled1;
746#[doc = "INTR (r) register accessor: Raw Interrupts
747
748You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
749
750For information about available fields see [`mod@intr`]
751module"]
752pub type INTR = crate::Reg<intr::INTR_SPEC>;
753#[doc = "Raw Interrupts"]
754pub mod intr;
755#[doc = "INTE (rw) register accessor: Interrupt Enable
756
757You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
758
759For information about available fields see [`mod@inte`]
760module"]
761pub type INTE = crate::Reg<inte::INTE_SPEC>;
762#[doc = "Interrupt Enable"]
763pub mod inte;
764#[doc = "INTF (rw) register accessor: Interrupt Force
765
766You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
767
768For information about available fields see [`mod@intf`]
769module"]
770pub type INTF = crate::Reg<intf::INTF_SPEC>;
771#[doc = "Interrupt Force"]
772pub mod intf;
773#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing
774
775You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
776
777For information about available fields see [`mod@ints`]
778module"]
779pub type INTS = crate::Reg<ints::INTS_SPEC>;
780#[doc = "Interrupt status after masking & forcing"]
781pub mod ints;