rp2040_pac/io_qspi/
intr.rs

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1#[doc = "Register `INTR` reader"]
2pub type R = crate::R<INTR_SPEC>;
3#[doc = "Register `INTR` writer"]
4pub type W = crate::W<INTR_SPEC>;
5#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "]
6pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader;
7#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "]
8pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader;
9#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "]
10pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader;
11#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "]
12pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "]
14pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader;
15#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "]
16pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "]
18pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader;
19#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "]
20pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader;
21#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "]
22pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader;
23#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "]
24pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "]
26pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader;
27#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "]
28pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "]
30pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader;
31#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "]
32pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader;
33#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "]
34pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader;
35#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "]
36pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "]
38pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader;
39#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "]
40pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "]
42pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader;
43#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "]
44pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader;
45#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "]
46pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader;
47#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "]
48pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
49#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "]
50pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader;
51#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "]
52pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
53#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "]
54pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader;
55#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "]
56pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader;
57#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "]
58pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader;
59#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "]
60pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
61#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "]
62pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader;
63#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "]
64pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
65#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "]
66pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader;
67#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "]
68pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader;
69#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "]
70pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader;
71#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "]
72pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
73#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "]
74pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader;
75#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "]
76pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
77impl R {
78    #[doc = "Bit 0"]
79    #[inline(always)]
80    pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R {
81        GPIO_QSPI_SCLK_LEVEL_LOW_R::new((self.bits & 1) != 0)
82    }
83    #[doc = "Bit 1"]
84    #[inline(always)]
85    pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R {
86        GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0)
87    }
88    #[doc = "Bit 2"]
89    #[inline(always)]
90    pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R {
91        GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0)
92    }
93    #[doc = "Bit 3"]
94    #[inline(always)]
95    pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R {
96        GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0)
97    }
98    #[doc = "Bit 4"]
99    #[inline(always)]
100    pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R {
101        GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0)
102    }
103    #[doc = "Bit 5"]
104    #[inline(always)]
105    pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R {
106        GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0)
107    }
108    #[doc = "Bit 6"]
109    #[inline(always)]
110    pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R {
111        GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0)
112    }
113    #[doc = "Bit 7"]
114    #[inline(always)]
115    pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R {
116        GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0)
117    }
118    #[doc = "Bit 8"]
119    #[inline(always)]
120    pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R {
121        GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0)
122    }
123    #[doc = "Bit 9"]
124    #[inline(always)]
125    pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R {
126        GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0)
127    }
128    #[doc = "Bit 10"]
129    #[inline(always)]
130    pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R {
131        GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0)
132    }
133    #[doc = "Bit 11"]
134    #[inline(always)]
135    pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R {
136        GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0)
137    }
138    #[doc = "Bit 12"]
139    #[inline(always)]
140    pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R {
141        GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0)
142    }
143    #[doc = "Bit 13"]
144    #[inline(always)]
145    pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R {
146        GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0)
147    }
148    #[doc = "Bit 14"]
149    #[inline(always)]
150    pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R {
151        GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0)
152    }
153    #[doc = "Bit 15"]
154    #[inline(always)]
155    pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R {
156        GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0)
157    }
158    #[doc = "Bit 16"]
159    #[inline(always)]
160    pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R {
161        GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0)
162    }
163    #[doc = "Bit 17"]
164    #[inline(always)]
165    pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R {
166        GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0)
167    }
168    #[doc = "Bit 18"]
169    #[inline(always)]
170    pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R {
171        GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0)
172    }
173    #[doc = "Bit 19"]
174    #[inline(always)]
175    pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R {
176        GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0)
177    }
178    #[doc = "Bit 20"]
179    #[inline(always)]
180    pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R {
181        GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0)
182    }
183    #[doc = "Bit 21"]
184    #[inline(always)]
185    pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R {
186        GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0)
187    }
188    #[doc = "Bit 22"]
189    #[inline(always)]
190    pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R {
191        GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0)
192    }
193    #[doc = "Bit 23"]
194    #[inline(always)]
195    pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R {
196        GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0)
197    }
198}
199impl W {
200    #[doc = "Bit 2"]
201    #[inline(always)]
202    #[must_use]
203    pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<INTR_SPEC> {
204        GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 2)
205    }
206    #[doc = "Bit 3"]
207    #[inline(always)]
208    #[must_use]
209    pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<INTR_SPEC> {
210        GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 3)
211    }
212    #[doc = "Bit 6"]
213    #[inline(always)]
214    #[must_use]
215    pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<INTR_SPEC> {
216        GPIO_QSPI_SS_EDGE_LOW_W::new(self, 6)
217    }
218    #[doc = "Bit 7"]
219    #[inline(always)]
220    #[must_use]
221    pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<INTR_SPEC> {
222        GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 7)
223    }
224    #[doc = "Bit 10"]
225    #[inline(always)]
226    #[must_use]
227    pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<INTR_SPEC> {
228        GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 10)
229    }
230    #[doc = "Bit 11"]
231    #[inline(always)]
232    #[must_use]
233    pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<INTR_SPEC> {
234        GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 11)
235    }
236    #[doc = "Bit 14"]
237    #[inline(always)]
238    #[must_use]
239    pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<INTR_SPEC> {
240        GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 14)
241    }
242    #[doc = "Bit 15"]
243    #[inline(always)]
244    #[must_use]
245    pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<INTR_SPEC> {
246        GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 15)
247    }
248    #[doc = "Bit 18"]
249    #[inline(always)]
250    #[must_use]
251    pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<INTR_SPEC> {
252        GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 18)
253    }
254    #[doc = "Bit 19"]
255    #[inline(always)]
256    #[must_use]
257    pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<INTR_SPEC> {
258        GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 19)
259    }
260    #[doc = "Bit 22"]
261    #[inline(always)]
262    #[must_use]
263    pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<INTR_SPEC> {
264        GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 22)
265    }
266    #[doc = "Bit 23"]
267    #[inline(always)]
268    #[must_use]
269    pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<INTR_SPEC> {
270        GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 23)
271    }
272    #[doc = r" Writes raw bits to the register."]
273    #[doc = r""]
274    #[doc = r" # Safety"]
275    #[doc = r""]
276    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
277    #[inline(always)]
278    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
279        self.bits = bits;
280        self
281    }
282}
283#[doc = "Raw Interrupts  
284
285You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
286pub struct INTR_SPEC;
287impl crate::RegisterSpec for INTR_SPEC {
288    type Ux = u32;
289}
290#[doc = "`read()` method returns [`intr::R`](R) reader structure"]
291impl crate::Readable for INTR_SPEC {}
292#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"]
293impl crate::Writable for INTR_SPEC {
294    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
295    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00cc_cccc;
296}
297#[doc = "`reset()` method sets INTR to value 0"]
298impl crate::Resettable for INTR_SPEC {
299    const RESET_VALUE: u32 = 0;
300}
rp2040_pac/io_qspi/intr.rs

rp2040_pac/io_qspi/
intr.rs
