rp2040_pac/xip_ssi/
ctrlr0.rs

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1#[doc = "Register `CTRLR0` reader"]
2pub type R = crate::R<CTRLR0_SPEC>;
3#[doc = "Register `CTRLR0` writer"]
4pub type W = crate::W<CTRLR0_SPEC>;
5#[doc = "Field `DFS` reader - Data frame size"]
6pub type DFS_R = crate::FieldReader;
7#[doc = "Field `DFS` writer - Data frame size"]
8pub type DFS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `FRF` reader - Frame format"]
10pub type FRF_R = crate::FieldReader;
11#[doc = "Field `FRF` writer - Frame format"]
12pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `SCPH` reader - Serial clock phase"]
14pub type SCPH_R = crate::BitReader;
15#[doc = "Field `SCPH` writer - Serial clock phase"]
16pub type SCPH_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SCPOL` reader - Serial clock polarity"]
18pub type SCPOL_R = crate::BitReader;
19#[doc = "Field `SCPOL` writer - Serial clock polarity"]
20pub type SCPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TMOD` reader - Transfer mode"]
22pub type TMOD_R = crate::FieldReader<TMOD_A>;
23#[doc = "Transfer mode  
24
25Value on reset: 0"]
26#[derive(Clone, Copy, Debug, PartialEq, Eq)]
27#[repr(u8)]
28pub enum TMOD_A {
29    #[doc = "0: Both transmit and receive"]
30    TX_AND_RX = 0,
31    #[doc = "1: Transmit only (not for FRF == 0, standard SPI mode)"]
32    TX_ONLY = 1,
33    #[doc = "2: Receive only (not for FRF == 0, standard SPI mode)"]
34    RX_ONLY = 2,
35    #[doc = "3: EEPROM read mode (TX then RX; RX starts after control data TX'd)"]
36    EEPROM_READ = 3,
37}
38impl From<TMOD_A> for u8 {
39    #[inline(always)]
40    fn from(variant: TMOD_A) -> Self {
41        variant as _
42    }
43}
44impl crate::FieldSpec for TMOD_A {
45    type Ux = u8;
46}
47impl TMOD_R {
48    #[doc = "Get enumerated values variant"]
49    #[inline(always)]
50    pub const fn variant(&self) -> TMOD_A {
51        match self.bits {
52            0 => TMOD_A::TX_AND_RX,
53            1 => TMOD_A::TX_ONLY,
54            2 => TMOD_A::RX_ONLY,
55            3 => TMOD_A::EEPROM_READ,
56            _ => unreachable!(),
57        }
58    }
59    #[doc = "Both transmit and receive"]
60    #[inline(always)]
61    pub fn is_tx_and_rx(&self) -> bool {
62        *self == TMOD_A::TX_AND_RX
63    }
64    #[doc = "Transmit only (not for FRF == 0, standard SPI mode)"]
65    #[inline(always)]
66    pub fn is_tx_only(&self) -> bool {
67        *self == TMOD_A::TX_ONLY
68    }
69    #[doc = "Receive only (not for FRF == 0, standard SPI mode)"]
70    #[inline(always)]
71    pub fn is_rx_only(&self) -> bool {
72        *self == TMOD_A::RX_ONLY
73    }
74    #[doc = "EEPROM read mode (TX then RX; RX starts after control data TX'd)"]
75    #[inline(always)]
76    pub fn is_eeprom_read(&self) -> bool {
77        *self == TMOD_A::EEPROM_READ
78    }
79}
80#[doc = "Field `TMOD` writer - Transfer mode"]
81pub type TMOD_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, TMOD_A>;
82impl<'a, REG> TMOD_W<'a, REG>
83where
84    REG: crate::Writable + crate::RegisterSpec,
85    REG::Ux: From<u8>,
86{
87    #[doc = "Both transmit and receive"]
88    #[inline(always)]
89    pub fn tx_and_rx(self) -> &'a mut crate::W<REG> {
90        self.variant(TMOD_A::TX_AND_RX)
91    }
92    #[doc = "Transmit only (not for FRF == 0, standard SPI mode)"]
93    #[inline(always)]
94    pub fn tx_only(self) -> &'a mut crate::W<REG> {
95        self.variant(TMOD_A::TX_ONLY)
96    }
97    #[doc = "Receive only (not for FRF == 0, standard SPI mode)"]
98    #[inline(always)]
99    pub fn rx_only(self) -> &'a mut crate::W<REG> {
100        self.variant(TMOD_A::RX_ONLY)
101    }
102    #[doc = "EEPROM read mode (TX then RX; RX starts after control data TX'd)"]
103    #[inline(always)]
104    pub fn eeprom_read(self) -> &'a mut crate::W<REG> {
105        self.variant(TMOD_A::EEPROM_READ)
106    }
107}
108#[doc = "Field `SLV_OE` reader - Slave output enable"]
109pub type SLV_OE_R = crate::BitReader;
110#[doc = "Field `SLV_OE` writer - Slave output enable"]
111pub type SLV_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
112#[doc = "Field `SRL` reader - Shift register loop (test mode)"]
113pub type SRL_R = crate::BitReader;
114#[doc = "Field `SRL` writer - Shift register loop (test mode)"]
115pub type SRL_W<'a, REG> = crate::BitWriter<'a, REG>;
116#[doc = "Field `CFS` reader - Control frame size  
117 Value of n -> n+1 clocks per frame."]
118pub type CFS_R = crate::FieldReader;
119#[doc = "Field `CFS` writer - Control frame size  
120 Value of n -> n+1 clocks per frame."]
121pub type CFS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
122#[doc = "Field `DFS_32` reader - Data frame size in 32b transfer mode  
123 Value of n -> n+1 clocks per frame."]
124pub type DFS_32_R = crate::FieldReader;
125#[doc = "Field `DFS_32` writer - Data frame size in 32b transfer mode  
126 Value of n -> n+1 clocks per frame."]
127pub type DFS_32_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
128#[doc = "Field `SPI_FRF` reader - SPI frame format"]
129pub type SPI_FRF_R = crate::FieldReader<SPI_FRF_A>;
130#[doc = "SPI frame format  
131
132Value on reset: 0"]
133#[derive(Clone, Copy, Debug, PartialEq, Eq)]
134#[repr(u8)]
135pub enum SPI_FRF_A {
136    #[doc = "0: Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex"]
137    STD = 0,
138    #[doc = "1: Dual-SPI frame format; two bits per SCK, half-duplex"]
139    DUAL = 1,
140    #[doc = "2: Quad-SPI frame format; four bits per SCK, half-duplex"]
141    QUAD = 2,
142}
143impl From<SPI_FRF_A> for u8 {
144    #[inline(always)]
145    fn from(variant: SPI_FRF_A) -> Self {
146        variant as _
147    }
148}
149impl crate::FieldSpec for SPI_FRF_A {
150    type Ux = u8;
151}
152impl SPI_FRF_R {
153    #[doc = "Get enumerated values variant"]
154    #[inline(always)]
155    pub const fn variant(&self) -> Option<SPI_FRF_A> {
156        match self.bits {
157            0 => Some(SPI_FRF_A::STD),
158            1 => Some(SPI_FRF_A::DUAL),
159            2 => Some(SPI_FRF_A::QUAD),
160            _ => None,
161        }
162    }
163    #[doc = "Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex"]
164    #[inline(always)]
165    pub fn is_std(&self) -> bool {
166        *self == SPI_FRF_A::STD
167    }
168    #[doc = "Dual-SPI frame format; two bits per SCK, half-duplex"]
169    #[inline(always)]
170    pub fn is_dual(&self) -> bool {
171        *self == SPI_FRF_A::DUAL
172    }
173    #[doc = "Quad-SPI frame format; four bits per SCK, half-duplex"]
174    #[inline(always)]
175    pub fn is_quad(&self) -> bool {
176        *self == SPI_FRF_A::QUAD
177    }
178}
179#[doc = "Field `SPI_FRF` writer - SPI frame format"]
180pub type SPI_FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SPI_FRF_A>;
181impl<'a, REG> SPI_FRF_W<'a, REG>
182where
183    REG: crate::Writable + crate::RegisterSpec,
184    REG::Ux: From<u8>,
185{
186    #[doc = "Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex"]
187    #[inline(always)]
188    pub fn std(self) -> &'a mut crate::W<REG> {
189        self.variant(SPI_FRF_A::STD)
190    }
191    #[doc = "Dual-SPI frame format; two bits per SCK, half-duplex"]
192    #[inline(always)]
193    pub fn dual(self) -> &'a mut crate::W<REG> {
194        self.variant(SPI_FRF_A::DUAL)
195    }
196    #[doc = "Quad-SPI frame format; four bits per SCK, half-duplex"]
197    #[inline(always)]
198    pub fn quad(self) -> &'a mut crate::W<REG> {
199        self.variant(SPI_FRF_A::QUAD)
200    }
201}
202#[doc = "Field `SSTE` reader - Slave select toggle enable"]
203pub type SSTE_R = crate::BitReader;
204#[doc = "Field `SSTE` writer - Slave select toggle enable"]
205pub type SSTE_W<'a, REG> = crate::BitWriter<'a, REG>;
206impl R {
207    #[doc = "Bits 0:3 - Data frame size"]
208    #[inline(always)]
209    pub fn dfs(&self) -> DFS_R {
210        DFS_R::new((self.bits & 0x0f) as u8)
211    }
212    #[doc = "Bits 4:5 - Frame format"]
213    #[inline(always)]
214    pub fn frf(&self) -> FRF_R {
215        FRF_R::new(((self.bits >> 4) & 3) as u8)
216    }
217    #[doc = "Bit 6 - Serial clock phase"]
218    #[inline(always)]
219    pub fn scph(&self) -> SCPH_R {
220        SCPH_R::new(((self.bits >> 6) & 1) != 0)
221    }
222    #[doc = "Bit 7 - Serial clock polarity"]
223    #[inline(always)]
224    pub fn scpol(&self) -> SCPOL_R {
225        SCPOL_R::new(((self.bits >> 7) & 1) != 0)
226    }
227    #[doc = "Bits 8:9 - Transfer mode"]
228    #[inline(always)]
229    pub fn tmod(&self) -> TMOD_R {
230        TMOD_R::new(((self.bits >> 8) & 3) as u8)
231    }
232    #[doc = "Bit 10 - Slave output enable"]
233    #[inline(always)]
234    pub fn slv_oe(&self) -> SLV_OE_R {
235        SLV_OE_R::new(((self.bits >> 10) & 1) != 0)
236    }
237    #[doc = "Bit 11 - Shift register loop (test mode)"]
238    #[inline(always)]
239    pub fn srl(&self) -> SRL_R {
240        SRL_R::new(((self.bits >> 11) & 1) != 0)
241    }
242    #[doc = "Bits 12:15 - Control frame size  
243 Value of n -> n+1 clocks per frame."]
244    #[inline(always)]
245    pub fn cfs(&self) -> CFS_R {
246        CFS_R::new(((self.bits >> 12) & 0x0f) as u8)
247    }
248    #[doc = "Bits 16:20 - Data frame size in 32b transfer mode  
249 Value of n -> n+1 clocks per frame."]
250    #[inline(always)]
251    pub fn dfs_32(&self) -> DFS_32_R {
252        DFS_32_R::new(((self.bits >> 16) & 0x1f) as u8)
253    }
254    #[doc = "Bits 21:22 - SPI frame format"]
255    #[inline(always)]
256    pub fn spi_frf(&self) -> SPI_FRF_R {
257        SPI_FRF_R::new(((self.bits >> 21) & 3) as u8)
258    }
259    #[doc = "Bit 24 - Slave select toggle enable"]
260    #[inline(always)]
261    pub fn sste(&self) -> SSTE_R {
262        SSTE_R::new(((self.bits >> 24) & 1) != 0)
263    }
264}
265impl W {
266    #[doc = "Bits 0:3 - Data frame size"]
267    #[inline(always)]
268    #[must_use]
269    pub fn dfs(&mut self) -> DFS_W<CTRLR0_SPEC> {
270        DFS_W::new(self, 0)
271    }
272    #[doc = "Bits 4:5 - Frame format"]
273    #[inline(always)]
274    #[must_use]
275    pub fn frf(&mut self) -> FRF_W<CTRLR0_SPEC> {
276        FRF_W::new(self, 4)
277    }
278    #[doc = "Bit 6 - Serial clock phase"]
279    #[inline(always)]
280    #[must_use]
281    pub fn scph(&mut self) -> SCPH_W<CTRLR0_SPEC> {
282        SCPH_W::new(self, 6)
283    }
284    #[doc = "Bit 7 - Serial clock polarity"]
285    #[inline(always)]
286    #[must_use]
287    pub fn scpol(&mut self) -> SCPOL_W<CTRLR0_SPEC> {
288        SCPOL_W::new(self, 7)
289    }
290    #[doc = "Bits 8:9 - Transfer mode"]
291    #[inline(always)]
292    #[must_use]
293    pub fn tmod(&mut self) -> TMOD_W<CTRLR0_SPEC> {
294        TMOD_W::new(self, 8)
295    }
296    #[doc = "Bit 10 - Slave output enable"]
297    #[inline(always)]
298    #[must_use]
299    pub fn slv_oe(&mut self) -> SLV_OE_W<CTRLR0_SPEC> {
300        SLV_OE_W::new(self, 10)
301    }
302    #[doc = "Bit 11 - Shift register loop (test mode)"]
303    #[inline(always)]
304    #[must_use]
305    pub fn srl(&mut self) -> SRL_W<CTRLR0_SPEC> {
306        SRL_W::new(self, 11)
307    }
308    #[doc = "Bits 12:15 - Control frame size  
309 Value of n -> n+1 clocks per frame."]
310    #[inline(always)]
311    #[must_use]
312    pub fn cfs(&mut self) -> CFS_W<CTRLR0_SPEC> {
313        CFS_W::new(self, 12)
314    }
315    #[doc = "Bits 16:20 - Data frame size in 32b transfer mode  
316 Value of n -> n+1 clocks per frame."]
317    #[inline(always)]
318    #[must_use]
319    pub fn dfs_32(&mut self) -> DFS_32_W<CTRLR0_SPEC> {
320        DFS_32_W::new(self, 16)
321    }
322    #[doc = "Bits 21:22 - SPI frame format"]
323    #[inline(always)]
324    #[must_use]
325    pub fn spi_frf(&mut self) -> SPI_FRF_W<CTRLR0_SPEC> {
326        SPI_FRF_W::new(self, 21)
327    }
328    #[doc = "Bit 24 - Slave select toggle enable"]
329    #[inline(always)]
330    #[must_use]
331    pub fn sste(&mut self) -> SSTE_W<CTRLR0_SPEC> {
332        SSTE_W::new(self, 24)
333    }
334    #[doc = r" Writes raw bits to the register."]
335    #[doc = r""]
336    #[doc = r" # Safety"]
337    #[doc = r""]
338    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
339    #[inline(always)]
340    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
341        self.bits = bits;
342        self
343    }
344}
345#[doc = "Control register 0  
346
347You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
348pub struct CTRLR0_SPEC;
349impl crate::RegisterSpec for CTRLR0_SPEC {
350    type Ux = u32;
351}
352#[doc = "`read()` method returns [`ctrlr0::R`](R) reader structure"]
353impl crate::Readable for CTRLR0_SPEC {}
354#[doc = "`write(|w| ..)` method takes [`ctrlr0::W`](W) writer structure"]
355impl crate::Writable for CTRLR0_SPEC {
356    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
357    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
358}
359#[doc = "`reset()` method sets CTRLR0 to value 0"]
360impl crate::Resettable for CTRLR0_SPEC {
361    const RESET_VALUE: u32 = 0;
362}
rp2040_pac/xip_ssi/ctrlr0.rs

rp2040_pac/xip_ssi/
ctrlr0.rs
