rp2040_pac/
pll_sys.rs

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1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    cs: CS,
5    pwr: PWR,
6    fbdiv_int: FBDIV_INT,
7    prim: PRIM,
8}
9impl RegisterBlock {
10    #[doc = "0x00 - Control and Status  
11 GENERAL CONSTRAINTS:  
12 Reference clock frequency min=5MHz, max=800MHz  
13 Feedback divider min=16, max=320  
14 VCO frequency min=750MHz, max=1600MHz"]
15    #[inline(always)]
16    pub const fn cs(&self) -> &CS {
17        &self.cs
18    }
19    #[doc = "0x04 - Controls the PLL power modes."]
20    #[inline(always)]
21    pub const fn pwr(&self) -> &PWR {
22        &self.pwr
23    }
24    #[doc = "0x08 - Feedback divisor  
25 (note: this PLL does not support fractional division)"]
26    #[inline(always)]
27    pub const fn fbdiv_int(&self) -> &FBDIV_INT {
28        &self.fbdiv_int
29    }
30    #[doc = "0x0c - Controls the PLL post dividers for the primary output  
31 (note: this PLL does not have a secondary output)  
32 the primary output is driven from VCO divided by postdiv1*postdiv2"]
33    #[inline(always)]
34    pub const fn prim(&self) -> &PRIM {
35        &self.prim
36    }
37}
38#[doc = "CS (rw) register accessor: Control and Status  
39 GENERAL CONSTRAINTS:  
40 Reference clock frequency min=5MHz, max=800MHz  
41 Feedback divider min=16, max=320  
42 VCO frequency min=750MHz, max=1600MHz  
43
44You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
45
46For information about available fields see [`mod@cs`]
47module"]
48pub type CS = crate::Reg<cs::CS_SPEC>;
49#[doc = "Control and Status  
50 GENERAL CONSTRAINTS:  
51 Reference clock frequency min=5MHz, max=800MHz  
52 Feedback divider min=16, max=320  
53 VCO frequency min=750MHz, max=1600MHz"]
54pub mod cs;
55#[doc = "PWR (rw) register accessor: Controls the PLL power modes.  
56
57You can [`read`](crate::generic::Reg::read) this register and get [`pwr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
58
59For information about available fields see [`mod@pwr`]
60module"]
61pub type PWR = crate::Reg<pwr::PWR_SPEC>;
62#[doc = "Controls the PLL power modes."]
63pub mod pwr;
64#[doc = "FBDIV_INT (rw) register accessor: Feedback divisor  
65 (note: this PLL does not support fractional division)  
66
67You can [`read`](crate::generic::Reg::read) this register and get [`fbdiv_int::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbdiv_int::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
68
69For information about available fields see [`mod@fbdiv_int`]
70module"]
71pub type FBDIV_INT = crate::Reg<fbdiv_int::FBDIV_INT_SPEC>;
72#[doc = "Feedback divisor  
73 (note: this PLL does not support fractional division)"]
74pub mod fbdiv_int;
75#[doc = "PRIM (rw) register accessor: Controls the PLL post dividers for the primary output  
76 (note: this PLL does not have a secondary output)  
77 the primary output is driven from VCO divided by postdiv1*postdiv2  
78
79You can [`read`](crate::generic::Reg::read) this register and get [`prim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
80
81For information about available fields see [`mod@prim`]
82module"]
83pub type PRIM = crate::Reg<prim::PRIM_SPEC>;
84#[doc = "Controls the PLL post dividers for the primary output  
85 (note: this PLL does not have a secondary output)  
86 the primary output is driven from VCO divided by postdiv1*postdiv2"]
87pub mod prim;
rp2040_pac/pll_sys.rs

rp2040_pac/
pll_sys.rs
