rp2040_pac/ppb/
icsr.rs

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1#[doc = "Register `ICSR` reader"]
2pub type R = crate::R<ICSR_SPEC>;
3#[doc = "Register `ICSR` writer"]
4pub type W = crate::W<ICSR_SPEC>;
5#[doc = "Field `VECTACTIVE` reader - Active exception number field. Reset clears the VECTACTIVE field."]
6pub type VECTACTIVE_R = crate::FieldReader<u16>;
7#[doc = "Field `VECTPENDING` reader - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier."]
8pub type VECTPENDING_R = crate::FieldReader<u16>;
9#[doc = "Field `ISRPENDING` reader - External interrupt pending flag"]
10pub type ISRPENDING_R = crate::BitReader;
11#[doc = "Field `ISRPREEMPT` reader - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced."]
12pub type ISRPREEMPT_R = crate::BitReader;
13#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit.  
14 Write:  
15 0 = No effect.  
16 1 = Removes the pending state from the SysTick exception.  
17 This bit is WO. On a register read its value is Unknown."]
18pub type PENDSTCLR_R = crate::BitReader;
19#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit.  
20 Write:  
21 0 = No effect.  
22 1 = Removes the pending state from the SysTick exception.  
23 This bit is WO. On a register read its value is Unknown."]
24pub type PENDSTCLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit.  
26 Write:  
27 0 = No effect.  
28 1 = Changes SysTick exception state to pending.  
29 Read:  
30 0 = SysTick exception is not pending.  
31 1 = SysTick exception is pending."]
32pub type PENDSTSET_R = crate::BitReader;
33#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit.  
34 Write:  
35 0 = No effect.  
36 1 = Changes SysTick exception state to pending.  
37 Read:  
38 0 = SysTick exception is not pending.  
39 1 = SysTick exception is pending."]
40pub type PENDSTSET_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit.  
42 Write:  
43 0 = No effect.  
44 1 = Removes the pending state from the PendSV exception."]
45pub type PENDSVCLR_R = crate::BitReader;
46#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit.  
47 Write:  
48 0 = No effect.  
49 1 = Removes the pending state from the PendSV exception."]
50pub type PENDSVCLR_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit.  
52 Write:  
53 0 = No effect.  
54 1 = Changes PendSV exception state to pending.  
55 Read:  
56 0 = PendSV exception is not pending.  
57 1 = PendSV exception is pending.  
58 Writing 1 to this bit is the only way to set the PendSV exception state to pending."]
59pub type PENDSVSET_R = crate::BitReader;
60#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit.  
61 Write:  
62 0 = No effect.  
63 1 = Changes PendSV exception state to pending.  
64 Read:  
65 0 = PendSV exception is not pending.  
66 1 = PendSV exception is pending.  
67 Writing 1 to this bit is the only way to set the PendSV exception state to pending."]
68pub type PENDSVSET_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `NMIPENDSET` reader - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.  
70 NMI set-pending bit.  
71 Write:  
72 0 = No effect.  
73 1 = Changes NMI exception state to pending.  
74 Read:  
75 0 = NMI exception is not pending.  
76 1 = NMI exception is pending.  
77 Because NMI is the highest-priority exception, normally the processor enters the NMI  
78 exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears  
79 this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the  
80 NMI signal is reasserted while the processor is executing that handler."]
81pub type NMIPENDSET_R = crate::BitReader;
82#[doc = "Field `NMIPENDSET` writer - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.  
83 NMI set-pending bit.  
84 Write:  
85 0 = No effect.  
86 1 = Changes NMI exception state to pending.  
87 Read:  
88 0 = NMI exception is not pending.  
89 1 = NMI exception is pending.  
90 Because NMI is the highest-priority exception, normally the processor enters the NMI  
91 exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears  
92 this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the  
93 NMI signal is reasserted while the processor is executing that handler."]
94pub type NMIPENDSET_W<'a, REG> = crate::BitWriter<'a, REG>;
95impl R {
96    #[doc = "Bits 0:8 - Active exception number field. Reset clears the VECTACTIVE field."]
97    #[inline(always)]
98    pub fn vectactive(&self) -> VECTACTIVE_R {
99        VECTACTIVE_R::new((self.bits & 0x01ff) as u16)
100    }
101    #[doc = "Bits 12:20 - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier."]
102    #[inline(always)]
103    pub fn vectpending(&self) -> VECTPENDING_R {
104        VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16)
105    }
106    #[doc = "Bit 22 - External interrupt pending flag"]
107    #[inline(always)]
108    pub fn isrpending(&self) -> ISRPENDING_R {
109        ISRPENDING_R::new(((self.bits >> 22) & 1) != 0)
110    }
111    #[doc = "Bit 23 - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced."]
112    #[inline(always)]
113    pub fn isrpreempt(&self) -> ISRPREEMPT_R {
114        ISRPREEMPT_R::new(((self.bits >> 23) & 1) != 0)
115    }
116    #[doc = "Bit 25 - SysTick exception clear-pending bit.  
117 Write:  
118 0 = No effect.  
119 1 = Removes the pending state from the SysTick exception.  
120 This bit is WO. On a register read its value is Unknown."]
121    #[inline(always)]
122    pub fn pendstclr(&self) -> PENDSTCLR_R {
123        PENDSTCLR_R::new(((self.bits >> 25) & 1) != 0)
124    }
125    #[doc = "Bit 26 - SysTick exception set-pending bit.  
126 Write:  
127 0 = No effect.  
128 1 = Changes SysTick exception state to pending.  
129 Read:  
130 0 = SysTick exception is not pending.  
131 1 = SysTick exception is pending."]
132    #[inline(always)]
133    pub fn pendstset(&self) -> PENDSTSET_R {
134        PENDSTSET_R::new(((self.bits >> 26) & 1) != 0)
135    }
136    #[doc = "Bit 27 - PendSV clear-pending bit.  
137 Write:  
138 0 = No effect.  
139 1 = Removes the pending state from the PendSV exception."]
140    #[inline(always)]
141    pub fn pendsvclr(&self) -> PENDSVCLR_R {
142        PENDSVCLR_R::new(((self.bits >> 27) & 1) != 0)
143    }
144    #[doc = "Bit 28 - PendSV set-pending bit.  
145 Write:  
146 0 = No effect.  
147 1 = Changes PendSV exception state to pending.  
148 Read:  
149 0 = PendSV exception is not pending.  
150 1 = PendSV exception is pending.  
151 Writing 1 to this bit is the only way to set the PendSV exception state to pending."]
152    #[inline(always)]
153    pub fn pendsvset(&self) -> PENDSVSET_R {
154        PENDSVSET_R::new(((self.bits >> 28) & 1) != 0)
155    }
156    #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.  
157 NMI set-pending bit.  
158 Write:  
159 0 = No effect.  
160 1 = Changes NMI exception state to pending.  
161 Read:  
162 0 = NMI exception is not pending.  
163 1 = NMI exception is pending.  
164 Because NMI is the highest-priority exception, normally the processor enters the NMI  
165 exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears  
166 this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the  
167 NMI signal is reasserted while the processor is executing that handler."]
168    #[inline(always)]
169    pub fn nmipendset(&self) -> NMIPENDSET_R {
170        NMIPENDSET_R::new(((self.bits >> 31) & 1) != 0)
171    }
172}
173impl W {
174    #[doc = "Bit 25 - SysTick exception clear-pending bit.  
175 Write:  
176 0 = No effect.  
177 1 = Removes the pending state from the SysTick exception.  
178 This bit is WO. On a register read its value is Unknown."]
179    #[inline(always)]
180    #[must_use]
181    pub fn pendstclr(&mut self) -> PENDSTCLR_W<ICSR_SPEC> {
182        PENDSTCLR_W::new(self, 25)
183    }
184    #[doc = "Bit 26 - SysTick exception set-pending bit.  
185 Write:  
186 0 = No effect.  
187 1 = Changes SysTick exception state to pending.  
188 Read:  
189 0 = SysTick exception is not pending.  
190 1 = SysTick exception is pending."]
191    #[inline(always)]
192    #[must_use]
193    pub fn pendstset(&mut self) -> PENDSTSET_W<ICSR_SPEC> {
194        PENDSTSET_W::new(self, 26)
195    }
196    #[doc = "Bit 27 - PendSV clear-pending bit.  
197 Write:  
198 0 = No effect.  
199 1 = Removes the pending state from the PendSV exception."]
200    #[inline(always)]
201    #[must_use]
202    pub fn pendsvclr(&mut self) -> PENDSVCLR_W<ICSR_SPEC> {
203        PENDSVCLR_W::new(self, 27)
204    }
205    #[doc = "Bit 28 - PendSV set-pending bit.  
206 Write:  
207 0 = No effect.  
208 1 = Changes PendSV exception state to pending.  
209 Read:  
210 0 = PendSV exception is not pending.  
211 1 = PendSV exception is pending.  
212 Writing 1 to this bit is the only way to set the PendSV exception state to pending."]
213    #[inline(always)]
214    #[must_use]
215    pub fn pendsvset(&mut self) -> PENDSVSET_W<ICSR_SPEC> {
216        PENDSVSET_W::new(self, 28)
217    }
218    #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.  
219 NMI set-pending bit.  
220 Write:  
221 0 = No effect.  
222 1 = Changes NMI exception state to pending.  
223 Read:  
224 0 = NMI exception is not pending.  
225 1 = NMI exception is pending.  
226 Because NMI is the highest-priority exception, normally the processor enters the NMI  
227 exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears  
228 this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the  
229 NMI signal is reasserted while the processor is executing that handler."]
230    #[inline(always)]
231    #[must_use]
232    pub fn nmipendset(&mut self) -> NMIPENDSET_W<ICSR_SPEC> {
233        NMIPENDSET_W::new(self, 31)
234    }
235    #[doc = r" Writes raw bits to the register."]
236    #[doc = r""]
237    #[doc = r" # Safety"]
238    #[doc = r""]
239    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
240    #[inline(always)]
241    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
242        self.bits = bits;
243        self
244    }
245}
246#[doc = "Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.  
247
248You can [`read`](crate::generic::Reg::read) this register and get [`icsr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
249pub struct ICSR_SPEC;
250impl crate::RegisterSpec for ICSR_SPEC {
251    type Ux = u32;
252}
253#[doc = "`read()` method returns [`icsr::R`](R) reader structure"]
254impl crate::Readable for ICSR_SPEC {}
255#[doc = "`write(|w| ..)` method takes [`icsr::W`](W) writer structure"]
256impl crate::Writable for ICSR_SPEC {
257    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
258    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
259}
260#[doc = "`reset()` method sets ICSR to value 0"]
261impl crate::Resettable for ICSR_SPEC {
262    const RESET_VALUE: u32 = 0;
263}
rp2040_pac/ppb/icsr.rs

rp2040_pac/ppb/
icsr.rs
