rp2040_pac/uart0/
uartlcr_h.rs

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1#[doc = "Register `UARTLCR_H` reader"]
2pub type R = crate::R<UARTLCR_H_SPEC>;
3#[doc = "Register `UARTLCR_H` writer"]
4pub type W = crate::W<UARTLCR_H_SPEC>;
5#[doc = "Field `BRK` reader - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."]
6pub type BRK_R = crate::BitReader;
7#[doc = "Field `BRK` writer - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."]
8pub type BRK_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PEN` reader - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."]
10pub type PEN_R = crate::BitReader;
11#[doc = "Field `PEN` writer - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."]
12pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EPS` reader - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."]
14pub type EPS_R = crate::BitReader;
15#[doc = "Field `EPS` writer - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."]
16pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `STP2` reader - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."]
18pub type STP2_R = crate::BitReader;
19#[doc = "Field `STP2` writer - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."]
20pub type STP2_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FEN` reader - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."]
22pub type FEN_R = crate::BitReader;
23#[doc = "Field `FEN` writer - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."]
24pub type FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `WLEN` reader - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."]
26pub type WLEN_R = crate::FieldReader;
27#[doc = "Field `WLEN` writer - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."]
28pub type WLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `SPS` reader - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."]
30pub type SPS_R = crate::BitReader;
31#[doc = "Field `SPS` writer - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."]
32pub type SPS_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."]
35    #[inline(always)]
36    pub fn brk(&self) -> BRK_R {
37        BRK_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 1 - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."]
40    #[inline(always)]
41    pub fn pen(&self) -> PEN_R {
42        PEN_R::new(((self.bits >> 1) & 1) != 0)
43    }
44    #[doc = "Bit 2 - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."]
45    #[inline(always)]
46    pub fn eps(&self) -> EPS_R {
47        EPS_R::new(((self.bits >> 2) & 1) != 0)
48    }
49    #[doc = "Bit 3 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."]
50    #[inline(always)]
51    pub fn stp2(&self) -> STP2_R {
52        STP2_R::new(((self.bits >> 3) & 1) != 0)
53    }
54    #[doc = "Bit 4 - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."]
55    #[inline(always)]
56    pub fn fen(&self) -> FEN_R {
57        FEN_R::new(((self.bits >> 4) & 1) != 0)
58    }
59    #[doc = "Bits 5:6 - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."]
60    #[inline(always)]
61    pub fn wlen(&self) -> WLEN_R {
62        WLEN_R::new(((self.bits >> 5) & 3) as u8)
63    }
64    #[doc = "Bit 7 - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."]
65    #[inline(always)]
66    pub fn sps(&self) -> SPS_R {
67        SPS_R::new(((self.bits >> 7) & 1) != 0)
68    }
69}
70impl W {
71    #[doc = "Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."]
72    #[inline(always)]
73    #[must_use]
74    pub fn brk(&mut self) -> BRK_W<UARTLCR_H_SPEC> {
75        BRK_W::new(self, 0)
76    }
77    #[doc = "Bit 1 - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."]
78    #[inline(always)]
79    #[must_use]
80    pub fn pen(&mut self) -> PEN_W<UARTLCR_H_SPEC> {
81        PEN_W::new(self, 1)
82    }
83    #[doc = "Bit 2 - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."]
84    #[inline(always)]
85    #[must_use]
86    pub fn eps(&mut self) -> EPS_W<UARTLCR_H_SPEC> {
87        EPS_W::new(self, 2)
88    }
89    #[doc = "Bit 3 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."]
90    #[inline(always)]
91    #[must_use]
92    pub fn stp2(&mut self) -> STP2_W<UARTLCR_H_SPEC> {
93        STP2_W::new(self, 3)
94    }
95    #[doc = "Bit 4 - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."]
96    #[inline(always)]
97    #[must_use]
98    pub fn fen(&mut self) -> FEN_W<UARTLCR_H_SPEC> {
99        FEN_W::new(self, 4)
100    }
101    #[doc = "Bits 5:6 - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."]
102    #[inline(always)]
103    #[must_use]
104    pub fn wlen(&mut self) -> WLEN_W<UARTLCR_H_SPEC> {
105        WLEN_W::new(self, 5)
106    }
107    #[doc = "Bit 7 - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."]
108    #[inline(always)]
109    #[must_use]
110    pub fn sps(&mut self) -> SPS_W<UARTLCR_H_SPEC> {
111        SPS_W::new(self, 7)
112    }
113    #[doc = r" Writes raw bits to the register."]
114    #[doc = r""]
115    #[doc = r" # Safety"]
116    #[doc = r""]
117    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
118    #[inline(always)]
119    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
120        self.bits = bits;
121        self
122    }
123}
124#[doc = "Line Control Register, UARTLCR_H  
125
126You can [`read`](crate::generic::Reg::read) this register and get [`uartlcr_h::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartlcr_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
127pub struct UARTLCR_H_SPEC;
128impl crate::RegisterSpec for UARTLCR_H_SPEC {
129    type Ux = u32;
130}
131#[doc = "`read()` method returns [`uartlcr_h::R`](R) reader structure"]
132impl crate::Readable for UARTLCR_H_SPEC {}
133#[doc = "`write(|w| ..)` method takes [`uartlcr_h::W`](W) writer structure"]
134impl crate::Writable for UARTLCR_H_SPEC {
135    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
136    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
137}
138#[doc = "`reset()` method sets UARTLCR_H to value 0"]
139impl crate::Resettable for UARTLCR_H_SPEC {
140    const RESET_VALUE: u32 = 0;
141}
rp2040_pac/uart0/uartlcr_h.rs

rp2040_pac/uart0/
uartlcr_h.rs
