rp2040_pac/uart0/
uartfr.rs

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1#[doc = "Register `UARTFR` reader"]
2pub type R = crate::R<UARTFR_SPEC>;
3#[doc = "Field `CTS` reader - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."]
4pub type CTS_R = crate::BitReader;
5#[doc = "Field `DSR` reader - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."]
6pub type DSR_R = crate::BitReader;
7#[doc = "Field `DCD` reader - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW."]
8pub type DCD_R = crate::BitReader;
9#[doc = "Field `BUSY` reader - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not."]
10pub type BUSY_R = crate::BitReader;
11#[doc = "Field `RXFE` reader - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty."]
12pub type RXFE_R = crate::BitReader;
13#[doc = "Field `TXFF` reader - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full."]
14pub type TXFF_R = crate::BitReader;
15#[doc = "Field `RXFF` reader - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full."]
16pub type RXFF_R = crate::BitReader;
17#[doc = "Field `TXFE` reader - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register."]
18pub type TXFE_R = crate::BitReader;
19#[doc = "Field `RI` reader - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW."]
20pub type RI_R = crate::BitReader;
21impl R {
22    #[doc = "Bit 0 - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."]
23    #[inline(always)]
24    pub fn cts(&self) -> CTS_R {
25        CTS_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."]
28    #[inline(always)]
29    pub fn dsr(&self) -> DSR_R {
30        DSR_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW."]
33    #[inline(always)]
34    pub fn dcd(&self) -> DCD_R {
35        DCD_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not."]
38    #[inline(always)]
39    pub fn busy(&self) -> BUSY_R {
40        BUSY_R::new(((self.bits >> 3) & 1) != 0)
41    }
42    #[doc = "Bit 4 - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty."]
43    #[inline(always)]
44    pub fn rxfe(&self) -> RXFE_R {
45        RXFE_R::new(((self.bits >> 4) & 1) != 0)
46    }
47    #[doc = "Bit 5 - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full."]
48    #[inline(always)]
49    pub fn txff(&self) -> TXFF_R {
50        TXFF_R::new(((self.bits >> 5) & 1) != 0)
51    }
52    #[doc = "Bit 6 - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full."]
53    #[inline(always)]
54    pub fn rxff(&self) -> RXFF_R {
55        RXFF_R::new(((self.bits >> 6) & 1) != 0)
56    }
57    #[doc = "Bit 7 - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register."]
58    #[inline(always)]
59    pub fn txfe(&self) -> TXFE_R {
60        TXFE_R::new(((self.bits >> 7) & 1) != 0)
61    }
62    #[doc = "Bit 8 - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW."]
63    #[inline(always)]
64    pub fn ri(&self) -> RI_R {
65        RI_R::new(((self.bits >> 8) & 1) != 0)
66    }
67}
68#[doc = "Flag Register, UARTFR  
69
70You can [`read`](crate::generic::Reg::read) this register and get [`uartfr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
71pub struct UARTFR_SPEC;
72impl crate::RegisterSpec for UARTFR_SPEC {
73    type Ux = u32;
74}
75#[doc = "`read()` method returns [`uartfr::R`](R) reader structure"]
76impl crate::Readable for UARTFR_SPEC {}
77#[doc = "`reset()` method sets UARTFR to value 0x90"]
78impl crate::Resettable for UARTFR_SPEC {
79    const RESET_VALUE: u32 = 0x90;
80}
rp2040_pac/uart0/uartfr.rs

rp2040_pac/uart0/
uartfr.rs
