rp2040_pac/spi0/
sspimsc.rs

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1#[doc = "Register `SSPIMSC` reader"]
2pub type R = crate::R<SSPIMSC_SPEC>;
3#[doc = "Register `SSPIMSC` writer"]
4pub type W = crate::W<SSPIMSC_SPEC>;
5#[doc = "Field `RORIM` reader - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."]
6pub type RORIM_R = crate::BitReader;
7#[doc = "Field `RORIM` writer - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."]
8pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RTIM` reader - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."]
10pub type RTIM_R = crate::BitReader;
11#[doc = "Field `RTIM` writer - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."]
12pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXIM` reader - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."]
14pub type RXIM_R = crate::BitReader;
15#[doc = "Field `RXIM` writer - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."]
16pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TXIM` reader - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."]
18pub type TXIM_R = crate::BitReader;
19#[doc = "Field `TXIM` writer - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."]
20pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."]
23    #[inline(always)]
24    pub fn rorim(&self) -> RORIM_R {
25        RORIM_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."]
28    #[inline(always)]
29    pub fn rtim(&self) -> RTIM_R {
30        RTIM_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."]
33    #[inline(always)]
34    pub fn rxim(&self) -> RXIM_R {
35        RXIM_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."]
38    #[inline(always)]
39    pub fn txim(&self) -> TXIM_R {
40        TXIM_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bit 0 - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."]
45    #[inline(always)]
46    #[must_use]
47    pub fn rorim(&mut self) -> RORIM_W<SSPIMSC_SPEC> {
48        RORIM_W::new(self, 0)
49    }
50    #[doc = "Bit 1 - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."]
51    #[inline(always)]
52    #[must_use]
53    pub fn rtim(&mut self) -> RTIM_W<SSPIMSC_SPEC> {
54        RTIM_W::new(self, 1)
55    }
56    #[doc = "Bit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."]
57    #[inline(always)]
58    #[must_use]
59    pub fn rxim(&mut self) -> RXIM_W<SSPIMSC_SPEC> {
60        RXIM_W::new(self, 2)
61    }
62    #[doc = "Bit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."]
63    #[inline(always)]
64    #[must_use]
65    pub fn txim(&mut self) -> TXIM_W<SSPIMSC_SPEC> {
66        TXIM_W::new(self, 3)
67    }
68    #[doc = r" Writes raw bits to the register."]
69    #[doc = r""]
70    #[doc = r" # Safety"]
71    #[doc = r""]
72    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.bits = bits;
76        self
77    }
78}
79#[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9  
80
81You can [`read`](crate::generic::Reg::read) this register and get [`sspimsc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspimsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
82pub struct SSPIMSC_SPEC;
83impl crate::RegisterSpec for SSPIMSC_SPEC {
84    type Ux = u32;
85}
86#[doc = "`read()` method returns [`sspimsc::R`](R) reader structure"]
87impl crate::Readable for SSPIMSC_SPEC {}
88#[doc = "`write(|w| ..)` method takes [`sspimsc::W`](W) writer structure"]
89impl crate::Writable for SSPIMSC_SPEC {
90    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
92}
93#[doc = "`reset()` method sets SSPIMSC to value 0"]
94impl crate::Resettable for SSPIMSC_SPEC {
95    const RESET_VALUE: u32 = 0;
96}
rp2040_pac/spi0/sspimsc.rs

rp2040_pac/spi0/
sspimsc.rs
