rp2040_pac/ppb/
mpu_ctrl.rs

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1#[doc = "Register `MPU_CTRL` reader"]
2pub type R = crate::R<MPU_CTRL_SPEC>;
3#[doc = "Register `MPU_CTRL` writer"]
4pub type W = crate::W<MPU_CTRL_SPEC>;
5#[doc = "Field `ENABLE` reader - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.  
6 0 = MPU disabled.  
7 1 = MPU enabled."]
8pub type ENABLE_R = crate::BitReader;
9#[doc = "Field `ENABLE` writer - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.  
10 0 = MPU disabled.  
11 1 = MPU enabled."]
12pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `HFNMIENA` reader - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.  
14 When the MPU is enabled:  
15 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.  
16 1 = the MPU is enabled during HardFault and NMI handlers."]
17pub type HFNMIENA_R = crate::BitReader;
18#[doc = "Field `HFNMIENA` writer - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.  
19 When the MPU is enabled:  
20 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.  
21 1 = the MPU is enabled during HardFault and NMI handlers."]
22pub type HFNMIENA_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `PRIVDEFENA` reader - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.  
24 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not  
25 covered by any enabled region causes a fault.  
26 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.  
27 When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."]
28pub type PRIVDEFENA_R = crate::BitReader;
29#[doc = "Field `PRIVDEFENA` writer - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.  
30 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not  
31 covered by any enabled region causes a fault.  
32 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.  
33 When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."]
34pub type PRIVDEFENA_W<'a, REG> = crate::BitWriter<'a, REG>;
35impl R {
36    #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.  
37 0 = MPU disabled.  
38 1 = MPU enabled."]
39    #[inline(always)]
40    pub fn enable(&self) -> ENABLE_R {
41        ENABLE_R::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.  
44 When the MPU is enabled:  
45 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.  
46 1 = the MPU is enabled during HardFault and NMI handlers."]
47    #[inline(always)]
48    pub fn hfnmiena(&self) -> HFNMIENA_R {
49        HFNMIENA_R::new(((self.bits >> 1) & 1) != 0)
50    }
51    #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.  
52 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not  
53 covered by any enabled region causes a fault.  
54 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.  
55 When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."]
56    #[inline(always)]
57    pub fn privdefena(&self) -> PRIVDEFENA_R {
58        PRIVDEFENA_R::new(((self.bits >> 2) & 1) != 0)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.  
63 0 = MPU disabled.  
64 1 = MPU enabled."]
65    #[inline(always)]
66    #[must_use]
67    pub fn enable(&mut self) -> ENABLE_W<MPU_CTRL_SPEC> {
68        ENABLE_W::new(self, 0)
69    }
70    #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.  
71 When the MPU is enabled:  
72 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.  
73 1 = the MPU is enabled during HardFault and NMI handlers."]
74    #[inline(always)]
75    #[must_use]
76    pub fn hfnmiena(&mut self) -> HFNMIENA_W<MPU_CTRL_SPEC> {
77        HFNMIENA_W::new(self, 1)
78    }
79    #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.  
80 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not  
81 covered by any enabled region causes a fault.  
82 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.  
83 When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."]
84    #[inline(always)]
85    #[must_use]
86    pub fn privdefena(&mut self) -> PRIVDEFENA_W<MPU_CTRL_SPEC> {
87        PRIVDEFENA_W::new(self, 2)
88    }
89    #[doc = r" Writes raw bits to the register."]
90    #[doc = r""]
91    #[doc = r" # Safety"]
92    #[doc = r""]
93    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
94    #[inline(always)]
95    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
96        self.bits = bits;
97        self
98    }
99}
100#[doc = "Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.  
101
102You can [`read`](crate::generic::Reg::read) this register and get [`mpu_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
103pub struct MPU_CTRL_SPEC;
104impl crate::RegisterSpec for MPU_CTRL_SPEC {
105    type Ux = u32;
106}
107#[doc = "`read()` method returns [`mpu_ctrl::R`](R) reader structure"]
108impl crate::Readable for MPU_CTRL_SPEC {}
109#[doc = "`write(|w| ..)` method takes [`mpu_ctrl::W`](W) writer structure"]
110impl crate::Writable for MPU_CTRL_SPEC {
111    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
112    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
113}
114#[doc = "`reset()` method sets MPU_CTRL to value 0"]
115impl crate::Resettable for MPU_CTRL_SPEC {
116    const RESET_VALUE: u32 = 0;
117}
rp2040_pac/ppb/mpu_ctrl.rs

rp2040_pac/ppb/
mpu_ctrl.rs
