1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 ic_con: IC_CON,
5 ic_tar: IC_TAR,
6 ic_sar: IC_SAR,
7 _reserved3: [u8; 0x04],
8 ic_data_cmd: IC_DATA_CMD,
9 ic_ss_scl_hcnt: IC_SS_SCL_HCNT,
10 ic_ss_scl_lcnt: IC_SS_SCL_LCNT,
11 ic_fs_scl_hcnt: IC_FS_SCL_HCNT,
12 ic_fs_scl_lcnt: IC_FS_SCL_LCNT,
13 _reserved8: [u8; 0x08],
14 ic_intr_stat: IC_INTR_STAT,
15 ic_intr_mask: IC_INTR_MASK,
16 ic_raw_intr_stat: IC_RAW_INTR_STAT,
17 ic_rx_tl: IC_RX_TL,
18 ic_tx_tl: IC_TX_TL,
19 ic_clr_intr: IC_CLR_INTR,
20 ic_clr_rx_under: IC_CLR_RX_UNDER,
21 ic_clr_rx_over: IC_CLR_RX_OVER,
22 ic_clr_tx_over: IC_CLR_TX_OVER,
23 ic_clr_rd_req: IC_CLR_RD_REQ,
24 ic_clr_tx_abrt: IC_CLR_TX_ABRT,
25 ic_clr_rx_done: IC_CLR_RX_DONE,
26 ic_clr_activity: IC_CLR_ACTIVITY,
27 ic_clr_stop_det: IC_CLR_STOP_DET,
28 ic_clr_start_det: IC_CLR_START_DET,
29 ic_clr_gen_call: IC_CLR_GEN_CALL,
30 ic_enable: IC_ENABLE,
31 ic_status: IC_STATUS,
32 ic_txflr: IC_TXFLR,
33 ic_rxflr: IC_RXFLR,
34 ic_sda_hold: IC_SDA_HOLD,
35 ic_tx_abrt_source: IC_TX_ABRT_SOURCE,
36 ic_slv_data_nack_only: IC_SLV_DATA_NACK_ONLY,
37 ic_dma_cr: IC_DMA_CR,
38 ic_dma_tdlr: IC_DMA_TDLR,
39 ic_dma_rdlr: IC_DMA_RDLR,
40 ic_sda_setup: IC_SDA_SETUP,
41 ic_ack_general_call: IC_ACK_GENERAL_CALL,
42 ic_enable_status: IC_ENABLE_STATUS,
43 ic_fs_spklen: IC_FS_SPKLEN,
44 _reserved38: [u8; 0x04],
45 ic_clr_restart_det: IC_CLR_RESTART_DET,
46 _reserved39: [u8; 0x48],
47 ic_comp_param_1: IC_COMP_PARAM_1,
48 ic_comp_version: IC_COMP_VERSION,
49 ic_comp_type: IC_COMP_TYPE,
50}
51impl RegisterBlock {
52 #[doc = "0x00 - I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\]
53register being set to 0. Writes at other times have no effect.
54
55 Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."]
56 #[inline(always)]
57 pub const fn ic_con(&self) -> &IC_CON {
58 &self.ic_con
59 }
60 #[doc = "0x04 - I2C Target Address Register
61
62 This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\]
63is set to 0.
64
65 Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."]
66 #[inline(always)]
67 pub const fn ic_tar(&self) -> &IC_TAR {
68 &self.ic_tar
69 }
70 #[doc = "0x08 - I2C Slave Address Register"]
71 #[inline(always)]
72 pub const fn ic_sar(&self) -> &IC_SAR {
73 &self.ic_sar
74 }
75 #[doc = "0x10 - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
76
77 The size of the register changes as follows:
78
79 Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."]
80 #[inline(always)]
81 pub const fn ic_data_cmd(&self) -> &IC_DATA_CMD {
82 &self.ic_data_cmd
83 }
84 #[doc = "0x14 - Standard Speed I2C Clock SCL High Count Register"]
85 #[inline(always)]
86 pub const fn ic_ss_scl_hcnt(&self) -> &IC_SS_SCL_HCNT {
87 &self.ic_ss_scl_hcnt
88 }
89 #[doc = "0x18 - Standard Speed I2C Clock SCL Low Count Register"]
90 #[inline(always)]
91 pub const fn ic_ss_scl_lcnt(&self) -> &IC_SS_SCL_LCNT {
92 &self.ic_ss_scl_lcnt
93 }
94 #[doc = "0x1c - Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"]
95 #[inline(always)]
96 pub const fn ic_fs_scl_hcnt(&self) -> &IC_FS_SCL_HCNT {
97 &self.ic_fs_scl_hcnt
98 }
99 #[doc = "0x20 - Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"]
100 #[inline(always)]
101 pub const fn ic_fs_scl_lcnt(&self) -> &IC_FS_SCL_LCNT {
102 &self.ic_fs_scl_lcnt
103 }
104 #[doc = "0x2c - I2C Interrupt Status Register
105
106 Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."]
107 #[inline(always)]
108 pub const fn ic_intr_stat(&self) -> &IC_INTR_STAT {
109 &self.ic_intr_stat
110 }
111 #[doc = "0x30 - I2C Interrupt Mask Register.
112
113 These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."]
114 #[inline(always)]
115 pub const fn ic_intr_mask(&self) -> &IC_INTR_MASK {
116 &self.ic_intr_mask
117 }
118 #[doc = "0x34 - I2C Raw Interrupt Status Register
119
120 Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."]
121 #[inline(always)]
122 pub const fn ic_raw_intr_stat(&self) -> &IC_RAW_INTR_STAT {
123 &self.ic_raw_intr_stat
124 }
125 #[doc = "0x38 - I2C Receive FIFO Threshold Register"]
126 #[inline(always)]
127 pub const fn ic_rx_tl(&self) -> &IC_RX_TL {
128 &self.ic_rx_tl
129 }
130 #[doc = "0x3c - I2C Transmit FIFO Threshold Register"]
131 #[inline(always)]
132 pub const fn ic_tx_tl(&self) -> &IC_TX_TL {
133 &self.ic_tx_tl
134 }
135 #[doc = "0x40 - Clear Combined and Individual Interrupt Register"]
136 #[inline(always)]
137 pub const fn ic_clr_intr(&self) -> &IC_CLR_INTR {
138 &self.ic_clr_intr
139 }
140 #[doc = "0x44 - Clear RX_UNDER Interrupt Register"]
141 #[inline(always)]
142 pub const fn ic_clr_rx_under(&self) -> &IC_CLR_RX_UNDER {
143 &self.ic_clr_rx_under
144 }
145 #[doc = "0x48 - Clear RX_OVER Interrupt Register"]
146 #[inline(always)]
147 pub const fn ic_clr_rx_over(&self) -> &IC_CLR_RX_OVER {
148 &self.ic_clr_rx_over
149 }
150 #[doc = "0x4c - Clear TX_OVER Interrupt Register"]
151 #[inline(always)]
152 pub const fn ic_clr_tx_over(&self) -> &IC_CLR_TX_OVER {
153 &self.ic_clr_tx_over
154 }
155 #[doc = "0x50 - Clear RD_REQ Interrupt Register"]
156 #[inline(always)]
157 pub const fn ic_clr_rd_req(&self) -> &IC_CLR_RD_REQ {
158 &self.ic_clr_rd_req
159 }
160 #[doc = "0x54 - Clear TX_ABRT Interrupt Register"]
161 #[inline(always)]
162 pub const fn ic_clr_tx_abrt(&self) -> &IC_CLR_TX_ABRT {
163 &self.ic_clr_tx_abrt
164 }
165 #[doc = "0x58 - Clear RX_DONE Interrupt Register"]
166 #[inline(always)]
167 pub const fn ic_clr_rx_done(&self) -> &IC_CLR_RX_DONE {
168 &self.ic_clr_rx_done
169 }
170 #[doc = "0x5c - Clear ACTIVITY Interrupt Register"]
171 #[inline(always)]
172 pub const fn ic_clr_activity(&self) -> &IC_CLR_ACTIVITY {
173 &self.ic_clr_activity
174 }
175 #[doc = "0x60 - Clear STOP_DET Interrupt Register"]
176 #[inline(always)]
177 pub const fn ic_clr_stop_det(&self) -> &IC_CLR_STOP_DET {
178 &self.ic_clr_stop_det
179 }
180 #[doc = "0x64 - Clear START_DET Interrupt Register"]
181 #[inline(always)]
182 pub const fn ic_clr_start_det(&self) -> &IC_CLR_START_DET {
183 &self.ic_clr_start_det
184 }
185 #[doc = "0x68 - Clear GEN_CALL Interrupt Register"]
186 #[inline(always)]
187 pub const fn ic_clr_gen_call(&self) -> &IC_CLR_GEN_CALL {
188 &self.ic_clr_gen_call
189 }
190 #[doc = "0x6c - I2C Enable Register"]
191 #[inline(always)]
192 pub const fn ic_enable(&self) -> &IC_ENABLE {
193 &self.ic_enable
194 }
195 #[doc = "0x70 - I2C Status Register
196
197 This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.
198
199 When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"]
200 #[inline(always)]
201 pub const fn ic_status(&self) -> &IC_STATUS {
202 &self.ic_status
203 }
204 #[doc = "0x74 - I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."]
205 #[inline(always)]
206 pub const fn ic_txflr(&self) -> &IC_TXFLR {
207 &self.ic_txflr
208 }
209 #[doc = "0x78 - I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."]
210 #[inline(always)]
211 pub const fn ic_rxflr(&self) -> &IC_RXFLR {
212 &self.ic_rxflr
213 }
214 #[doc = "0x7c - I2C SDA Hold Time Length Register
215
216 The bits \\[15:0\\]
217of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).
218
219 The bits \\[23:16\\]
220of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.
221
222 Writes to this register succeed only when IC_ENABLE\\[0\\]=0.
223
224 The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.
225
226 The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."]
227 #[inline(always)]
228 pub const fn ic_sda_hold(&self) -> &IC_SDA_HOLD {
229 &self.ic_sda_hold
230 }
231 #[doc = "0x80 - I2C Transmit Abort Source Register
232
233 This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]).
234
235 Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."]
236 #[inline(always)]
237 pub const fn ic_tx_abrt_source(&self) -> &IC_TX_ABRT_SOURCE {
238 &self.ic_tx_abrt_source
239 }
240 #[doc = "0x84 - Generate Slave Data NACK Register
241
242 The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.
243
244 A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\]
245= 0) - Slave part is inactive (IC_STATUS\\[6\\]
246= 0) Note: The IC_STATUS\\[6\\]
247is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."]
248 #[inline(always)]
249 pub const fn ic_slv_data_nack_only(&self) -> &IC_SLV_DATA_NACK_ONLY {
250 &self.ic_slv_data_nack_only
251 }
252 #[doc = "0x88 - DMA Control Register
253
254 The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."]
255 #[inline(always)]
256 pub const fn ic_dma_cr(&self) -> &IC_DMA_CR {
257 &self.ic_dma_cr
258 }
259 #[doc = "0x8c - DMA Transmit Data Level Register"]
260 #[inline(always)]
261 pub const fn ic_dma_tdlr(&self) -> &IC_DMA_TDLR {
262 &self.ic_dma_tdlr
263 }
264 #[doc = "0x90 - I2C Receive Data Level Register"]
265 #[inline(always)]
266 pub const fn ic_dma_rdlr(&self) -> &IC_DMA_RDLR {
267 &self.ic_dma_rdlr
268 }
269 #[doc = "0x94 - I2C SDA Setup Register
270
271 This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.
272
273 Writes to this register succeed only when IC_ENABLE\\[0\\]
274= 0.
275
276 Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."]
277 #[inline(always)]
278 pub const fn ic_sda_setup(&self) -> &IC_SDA_SETUP {
279 &self.ic_sda_setup
280 }
281 #[doc = "0x98 - I2C ACK General Call Register
282
283 The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.
284
285 This register is applicable only when the DW_apb_i2c is in slave mode."]
286 #[inline(always)]
287 pub const fn ic_ack_general_call(&self) -> &IC_ACK_GENERAL_CALL {
288 &self.ic_ack_general_call
289 }
290 #[doc = "0x9c - I2C Enable Status Register
291
292 The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\]
293register is set from 1 to 0; that is, when DW_apb_i2c is disabled.
294
295 If IC_ENABLE\\[0\\]
296has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.
297
298 If IC_ENABLE\\[0\\]
299has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.
300
301 Note: When IC_ENABLE\\[0\\]
302has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."]
303 #[inline(always)]
304 pub const fn ic_enable_status(&self) -> &IC_ENABLE_STATUS {
305 &self.ic_enable_status
306 }
307 #[doc = "0xa0 - I2C SS, FS or FM+ spike suppression limit
308
309 This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."]
310 #[inline(always)]
311 pub const fn ic_fs_spklen(&self) -> &IC_FS_SPKLEN {
312 &self.ic_fs_spklen
313 }
314 #[doc = "0xa8 - Clear RESTART_DET Interrupt Register"]
315 #[inline(always)]
316 pub const fn ic_clr_restart_det(&self) -> &IC_CLR_RESTART_DET {
317 &self.ic_clr_restart_det
318 }
319 #[doc = "0xf4 - Component Parameter Register 1
320
321 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"]
322 #[inline(always)]
323 pub const fn ic_comp_param_1(&self) -> &IC_COMP_PARAM_1 {
324 &self.ic_comp_param_1
325 }
326 #[doc = "0xf8 - I2C Component Version Register"]
327 #[inline(always)]
328 pub const fn ic_comp_version(&self) -> &IC_COMP_VERSION {
329 &self.ic_comp_version
330 }
331 #[doc = "0xfc - I2C Component Type Register"]
332 #[inline(always)]
333 pub const fn ic_comp_type(&self) -> &IC_COMP_TYPE {
334 &self.ic_comp_type
335 }
336}
337#[doc = "IC_CON (rw) register accessor: I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\]
338register being set to 0. Writes at other times have no effect.
339
340 Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.
341
342You can [`read`](crate::generic::Reg::read) this register and get [`ic_con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
343
344For information about available fields see [`mod@ic_con`]
345module"]
346pub type IC_CON = crate::Reg<ic_con::IC_CON_SPEC>;
347#[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\]
348register being set to 0. Writes at other times have no effect.
349
350 Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."]
351pub mod ic_con;
352#[doc = "IC_TAR (rw) register accessor: I2C Target Address Register
353
354 This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\]
355is set to 0.
356
357 Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.
358
359You can [`read`](crate::generic::Reg::read) this register and get [`ic_tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
360
361For information about available fields see [`mod@ic_tar`]
362module"]
363pub type IC_TAR = crate::Reg<ic_tar::IC_TAR_SPEC>;
364#[doc = "I2C Target Address Register
365
366 This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\]
367is set to 0.
368
369 Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."]
370pub mod ic_tar;
371#[doc = "IC_SAR (rw) register accessor: I2C Slave Address Register
372
373You can [`read`](crate::generic::Reg::read) this register and get [`ic_sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
374
375For information about available fields see [`mod@ic_sar`]
376module"]
377pub type IC_SAR = crate::Reg<ic_sar::IC_SAR_SPEC>;
378#[doc = "I2C Slave Address Register"]
379pub mod ic_sar;
380#[doc = "IC_DATA_CMD (rw) register accessor: I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
381
382 The size of the register changes as follows:
383
384 Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.
385
386You can [`read`](crate::generic::Reg::read) this register and get [`ic_data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
387
388For information about available fields see [`mod@ic_data_cmd`]
389module"]
390pub type IC_DATA_CMD = crate::Reg<ic_data_cmd::IC_DATA_CMD_SPEC>;
391#[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
392
393 The size of the register changes as follows:
394
395 Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."]
396pub mod ic_data_cmd;
397#[doc = "IC_SS_SCL_HCNT (rw) register accessor: Standard Speed I2C Clock SCL High Count Register
398
399You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
400
401For information about available fields see [`mod@ic_ss_scl_hcnt`]
402module"]
403pub type IC_SS_SCL_HCNT = crate::Reg<ic_ss_scl_hcnt::IC_SS_SCL_HCNT_SPEC>;
404#[doc = "Standard Speed I2C Clock SCL High Count Register"]
405pub mod ic_ss_scl_hcnt;
406#[doc = "IC_SS_SCL_LCNT (rw) register accessor: Standard Speed I2C Clock SCL Low Count Register
407
408You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
409
410For information about available fields see [`mod@ic_ss_scl_lcnt`]
411module"]
412pub type IC_SS_SCL_LCNT = crate::Reg<ic_ss_scl_lcnt::IC_SS_SCL_LCNT_SPEC>;
413#[doc = "Standard Speed I2C Clock SCL Low Count Register"]
414pub mod ic_ss_scl_lcnt;
415#[doc = "IC_FS_SCL_HCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
416
417You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
418
419For information about available fields see [`mod@ic_fs_scl_hcnt`]
420module"]
421pub type IC_FS_SCL_HCNT = crate::Reg<ic_fs_scl_hcnt::IC_FS_SCL_HCNT_SPEC>;
422#[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"]
423pub mod ic_fs_scl_hcnt;
424#[doc = "IC_FS_SCL_LCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
425
426You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
427
428For information about available fields see [`mod@ic_fs_scl_lcnt`]
429module"]
430pub type IC_FS_SCL_LCNT = crate::Reg<ic_fs_scl_lcnt::IC_FS_SCL_LCNT_SPEC>;
431#[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"]
432pub mod ic_fs_scl_lcnt;
433#[doc = "IC_INTR_STAT (r) register accessor: I2C Interrupt Status Register
434
435 Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.
436
437You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
438
439For information about available fields see [`mod@ic_intr_stat`]
440module"]
441pub type IC_INTR_STAT = crate::Reg<ic_intr_stat::IC_INTR_STAT_SPEC>;
442#[doc = "I2C Interrupt Status Register
443
444 Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."]
445pub mod ic_intr_stat;
446#[doc = "IC_INTR_MASK (rw) register accessor: I2C Interrupt Mask Register.
447
448 These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.
449
450You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
451
452For information about available fields see [`mod@ic_intr_mask`]
453module"]
454pub type IC_INTR_MASK = crate::Reg<ic_intr_mask::IC_INTR_MASK_SPEC>;
455#[doc = "I2C Interrupt Mask Register.
456
457 These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."]
458pub mod ic_intr_mask;
459#[doc = "IC_RAW_INTR_STAT (r) register accessor: I2C Raw Interrupt Status Register
460
461 Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.
462
463You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
464
465For information about available fields see [`mod@ic_raw_intr_stat`]
466module"]
467pub type IC_RAW_INTR_STAT = crate::Reg<ic_raw_intr_stat::IC_RAW_INTR_STAT_SPEC>;
468#[doc = "I2C Raw Interrupt Status Register
469
470 Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."]
471pub mod ic_raw_intr_stat;
472#[doc = "IC_RX_TL (rw) register accessor: I2C Receive FIFO Threshold Register
473
474You can [`read`](crate::generic::Reg::read) this register and get [`ic_rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
475
476For information about available fields see [`mod@ic_rx_tl`]
477module"]
478pub type IC_RX_TL = crate::Reg<ic_rx_tl::IC_RX_TL_SPEC>;
479#[doc = "I2C Receive FIFO Threshold Register"]
480pub mod ic_rx_tl;
481#[doc = "IC_TX_TL (rw) register accessor: I2C Transmit FIFO Threshold Register
482
483You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
484
485For information about available fields see [`mod@ic_tx_tl`]
486module"]
487pub type IC_TX_TL = crate::Reg<ic_tx_tl::IC_TX_TL_SPEC>;
488#[doc = "I2C Transmit FIFO Threshold Register"]
489pub mod ic_tx_tl;
490#[doc = "IC_CLR_INTR (r) register accessor: Clear Combined and Individual Interrupt Register
491
492You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
493
494For information about available fields see [`mod@ic_clr_intr`]
495module"]
496pub type IC_CLR_INTR = crate::Reg<ic_clr_intr::IC_CLR_INTR_SPEC>;
497#[doc = "Clear Combined and Individual Interrupt Register"]
498pub mod ic_clr_intr;
499#[doc = "IC_CLR_RX_UNDER (r) register accessor: Clear RX_UNDER Interrupt Register
500
501You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_under::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
502
503For information about available fields see [`mod@ic_clr_rx_under`]
504module"]
505pub type IC_CLR_RX_UNDER = crate::Reg<ic_clr_rx_under::IC_CLR_RX_UNDER_SPEC>;
506#[doc = "Clear RX_UNDER Interrupt Register"]
507pub mod ic_clr_rx_under;
508#[doc = "IC_CLR_RX_OVER (r) register accessor: Clear RX_OVER Interrupt Register
509
510You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_over::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
511
512For information about available fields see [`mod@ic_clr_rx_over`]
513module"]
514pub type IC_CLR_RX_OVER = crate::Reg<ic_clr_rx_over::IC_CLR_RX_OVER_SPEC>;
515#[doc = "Clear RX_OVER Interrupt Register"]
516pub mod ic_clr_rx_over;
517#[doc = "IC_CLR_TX_OVER (r) register accessor: Clear TX_OVER Interrupt Register
518
519You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_over::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
520
521For information about available fields see [`mod@ic_clr_tx_over`]
522module"]
523pub type IC_CLR_TX_OVER = crate::Reg<ic_clr_tx_over::IC_CLR_TX_OVER_SPEC>;
524#[doc = "Clear TX_OVER Interrupt Register"]
525pub mod ic_clr_tx_over;
526#[doc = "IC_CLR_RD_REQ (r) register accessor: Clear RD_REQ Interrupt Register
527
528You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rd_req::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
529
530For information about available fields see [`mod@ic_clr_rd_req`]
531module"]
532pub type IC_CLR_RD_REQ = crate::Reg<ic_clr_rd_req::IC_CLR_RD_REQ_SPEC>;
533#[doc = "Clear RD_REQ Interrupt Register"]
534pub mod ic_clr_rd_req;
535#[doc = "IC_CLR_TX_ABRT (r) register accessor: Clear TX_ABRT Interrupt Register
536
537You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_abrt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
538
539For information about available fields see [`mod@ic_clr_tx_abrt`]
540module"]
541pub type IC_CLR_TX_ABRT = crate::Reg<ic_clr_tx_abrt::IC_CLR_TX_ABRT_SPEC>;
542#[doc = "Clear TX_ABRT Interrupt Register"]
543pub mod ic_clr_tx_abrt;
544#[doc = "IC_CLR_RX_DONE (r) register accessor: Clear RX_DONE Interrupt Register
545
546You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
547
548For information about available fields see [`mod@ic_clr_rx_done`]
549module"]
550pub type IC_CLR_RX_DONE = crate::Reg<ic_clr_rx_done::IC_CLR_RX_DONE_SPEC>;
551#[doc = "Clear RX_DONE Interrupt Register"]
552pub mod ic_clr_rx_done;
553#[doc = "IC_CLR_ACTIVITY (r) register accessor: Clear ACTIVITY Interrupt Register
554
555You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_activity::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
556
557For information about available fields see [`mod@ic_clr_activity`]
558module"]
559pub type IC_CLR_ACTIVITY = crate::Reg<ic_clr_activity::IC_CLR_ACTIVITY_SPEC>;
560#[doc = "Clear ACTIVITY Interrupt Register"]
561pub mod ic_clr_activity;
562#[doc = "IC_CLR_STOP_DET (r) register accessor: Clear STOP_DET Interrupt Register
563
564You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_stop_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
565
566For information about available fields see [`mod@ic_clr_stop_det`]
567module"]
568pub type IC_CLR_STOP_DET = crate::Reg<ic_clr_stop_det::IC_CLR_STOP_DET_SPEC>;
569#[doc = "Clear STOP_DET Interrupt Register"]
570pub mod ic_clr_stop_det;
571#[doc = "IC_CLR_START_DET (r) register accessor: Clear START_DET Interrupt Register
572
573You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_start_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
574
575For information about available fields see [`mod@ic_clr_start_det`]
576module"]
577pub type IC_CLR_START_DET = crate::Reg<ic_clr_start_det::IC_CLR_START_DET_SPEC>;
578#[doc = "Clear START_DET Interrupt Register"]
579pub mod ic_clr_start_det;
580#[doc = "IC_CLR_GEN_CALL (r) register accessor: Clear GEN_CALL Interrupt Register
581
582You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_gen_call::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
583
584For information about available fields see [`mod@ic_clr_gen_call`]
585module"]
586pub type IC_CLR_GEN_CALL = crate::Reg<ic_clr_gen_call::IC_CLR_GEN_CALL_SPEC>;
587#[doc = "Clear GEN_CALL Interrupt Register"]
588pub mod ic_clr_gen_call;
589#[doc = "IC_ENABLE (rw) register accessor: I2C Enable Register
590
591You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
592
593For information about available fields see [`mod@ic_enable`]
594module"]
595pub type IC_ENABLE = crate::Reg<ic_enable::IC_ENABLE_SPEC>;
596#[doc = "I2C Enable Register"]
597pub mod ic_enable;
598#[doc = "IC_STATUS (r) register accessor: I2C Status Register
599
600 This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.
601
602 When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0
603
604You can [`read`](crate::generic::Reg::read) this register and get [`ic_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
605
606For information about available fields see [`mod@ic_status`]
607module"]
608pub type IC_STATUS = crate::Reg<ic_status::IC_STATUS_SPEC>;
609#[doc = "I2C Status Register
610
611 This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.
612
613 When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"]
614pub mod ic_status;
615#[doc = "IC_TXFLR (r) register accessor: I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
616
617You can [`read`](crate::generic::Reg::read) this register and get [`ic_txflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
618
619For information about available fields see [`mod@ic_txflr`]
620module"]
621pub type IC_TXFLR = crate::Reg<ic_txflr::IC_TXFLR_SPEC>;
622#[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."]
623pub mod ic_txflr;
624#[doc = "IC_RXFLR (r) register accessor: I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
625
626You can [`read`](crate::generic::Reg::read) this register and get [`ic_rxflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
627
628For information about available fields see [`mod@ic_rxflr`]
629module"]
630pub type IC_RXFLR = crate::Reg<ic_rxflr::IC_RXFLR_SPEC>;
631#[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."]
632pub mod ic_rxflr;
633#[doc = "IC_SDA_HOLD (rw) register accessor: I2C SDA Hold Time Length Register
634
635 The bits \\[15:0\\]
636of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).
637
638 The bits \\[23:16\\]
639of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.
640
641 Writes to this register succeed only when IC_ENABLE\\[0\\]=0.
642
643 The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.
644
645 The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.
646
647You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
648
649For information about available fields see [`mod@ic_sda_hold`]
650module"]
651pub type IC_SDA_HOLD = crate::Reg<ic_sda_hold::IC_SDA_HOLD_SPEC>;
652#[doc = "I2C SDA Hold Time Length Register
653
654 The bits \\[15:0\\]
655of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).
656
657 The bits \\[23:16\\]
658of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.
659
660 Writes to this register succeed only when IC_ENABLE\\[0\\]=0.
661
662 The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.
663
664 The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."]
665pub mod ic_sda_hold;
666#[doc = "IC_TX_ABRT_SOURCE (r) register accessor: I2C Transmit Abort Source Register
667
668 This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]).
669
670 Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.
671
672You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_abrt_source::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
673
674For information about available fields see [`mod@ic_tx_abrt_source`]
675module"]
676pub type IC_TX_ABRT_SOURCE = crate::Reg<ic_tx_abrt_source::IC_TX_ABRT_SOURCE_SPEC>;
677#[doc = "I2C Transmit Abort Source Register
678
679 This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]).
680
681 Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."]
682pub mod ic_tx_abrt_source;
683#[doc = "IC_SLV_DATA_NACK_ONLY (rw) register accessor: Generate Slave Data NACK Register
684
685 The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.
686
687 A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\]
688= 0) - Slave part is inactive (IC_STATUS\\[6\\]
689= 0) Note: The IC_STATUS\\[6\\]
690is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.
691
692You can [`read`](crate::generic::Reg::read) this register and get [`ic_slv_data_nack_only::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
693
694For information about available fields see [`mod@ic_slv_data_nack_only`]
695module"]
696pub type IC_SLV_DATA_NACK_ONLY = crate::Reg<ic_slv_data_nack_only::IC_SLV_DATA_NACK_ONLY_SPEC>;
697#[doc = "Generate Slave Data NACK Register
698
699 The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.
700
701 A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\]
702= 0) - Slave part is inactive (IC_STATUS\\[6\\]
703= 0) Note: The IC_STATUS\\[6\\]
704is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."]
705pub mod ic_slv_data_nack_only;
706#[doc = "IC_DMA_CR (rw) register accessor: DMA Control Register
707
708 The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.
709
710You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
711
712For information about available fields see [`mod@ic_dma_cr`]
713module"]
714pub type IC_DMA_CR = crate::Reg<ic_dma_cr::IC_DMA_CR_SPEC>;
715#[doc = "DMA Control Register
716
717 The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."]
718pub mod ic_dma_cr;
719#[doc = "IC_DMA_TDLR (rw) register accessor: DMA Transmit Data Level Register
720
721You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_tdlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
722
723For information about available fields see [`mod@ic_dma_tdlr`]
724module"]
725pub type IC_DMA_TDLR = crate::Reg<ic_dma_tdlr::IC_DMA_TDLR_SPEC>;
726#[doc = "DMA Transmit Data Level Register"]
727pub mod ic_dma_tdlr;
728#[doc = "IC_DMA_RDLR (rw) register accessor: I2C Receive Data Level Register
729
730You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_rdlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
731
732For information about available fields see [`mod@ic_dma_rdlr`]
733module"]
734pub type IC_DMA_RDLR = crate::Reg<ic_dma_rdlr::IC_DMA_RDLR_SPEC>;
735#[doc = "I2C Receive Data Level Register"]
736pub mod ic_dma_rdlr;
737#[doc = "IC_SDA_SETUP (rw) register accessor: I2C SDA Setup Register
738
739 This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.
740
741 Writes to this register succeed only when IC_ENABLE\\[0\\]
742= 0.
743
744 Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.
745
746You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
747
748For information about available fields see [`mod@ic_sda_setup`]
749module"]
750pub type IC_SDA_SETUP = crate::Reg<ic_sda_setup::IC_SDA_SETUP_SPEC>;
751#[doc = "I2C SDA Setup Register
752
753 This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.
754
755 Writes to this register succeed only when IC_ENABLE\\[0\\]
756= 0.
757
758 Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."]
759pub mod ic_sda_setup;
760#[doc = "IC_ACK_GENERAL_CALL (rw) register accessor: I2C ACK General Call Register
761
762 The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.
763
764 This register is applicable only when the DW_apb_i2c is in slave mode.
765
766You can [`read`](crate::generic::Reg::read) this register and get [`ic_ack_general_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ack_general_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
767
768For information about available fields see [`mod@ic_ack_general_call`]
769module"]
770pub type IC_ACK_GENERAL_CALL = crate::Reg<ic_ack_general_call::IC_ACK_GENERAL_CALL_SPEC>;
771#[doc = "I2C ACK General Call Register
772
773 The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.
774
775 This register is applicable only when the DW_apb_i2c is in slave mode."]
776pub mod ic_ack_general_call;
777#[doc = "IC_ENABLE_STATUS (r) register accessor: I2C Enable Status Register
778
779 The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\]
780register is set from 1 to 0; that is, when DW_apb_i2c is disabled.
781
782 If IC_ENABLE\\[0\\]
783has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.
784
785 If IC_ENABLE\\[0\\]
786has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.
787
788 Note: When IC_ENABLE\\[0\\]
789has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.
790
791You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
792
793For information about available fields see [`mod@ic_enable_status`]
794module"]
795pub type IC_ENABLE_STATUS = crate::Reg<ic_enable_status::IC_ENABLE_STATUS_SPEC>;
796#[doc = "I2C Enable Status Register
797
798 The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\]
799register is set from 1 to 0; that is, when DW_apb_i2c is disabled.
800
801 If IC_ENABLE\\[0\\]
802has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.
803
804 If IC_ENABLE\\[0\\]
805has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.
806
807 Note: When IC_ENABLE\\[0\\]
808has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."]
809pub mod ic_enable_status;
810#[doc = "IC_FS_SPKLEN (rw) register accessor: I2C SS, FS or FM+ spike suppression limit
811
812 This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.
813
814You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_spklen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_spklen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
815
816For information about available fields see [`mod@ic_fs_spklen`]
817module"]
818pub type IC_FS_SPKLEN = crate::Reg<ic_fs_spklen::IC_FS_SPKLEN_SPEC>;
819#[doc = "I2C SS, FS or FM+ spike suppression limit
820
821 This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."]
822pub mod ic_fs_spklen;
823#[doc = "IC_CLR_RESTART_DET (r) register accessor: Clear RESTART_DET Interrupt Register
824
825You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_restart_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
826
827For information about available fields see [`mod@ic_clr_restart_det`]
828module"]
829pub type IC_CLR_RESTART_DET = crate::Reg<ic_clr_restart_det::IC_CLR_RESTART_DET_SPEC>;
830#[doc = "Clear RESTART_DET Interrupt Register"]
831pub mod ic_clr_restart_det;
832#[doc = "IC_COMP_PARAM_1 (r) register accessor: Component Parameter Register 1
833
834 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters
835
836You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
837
838For information about available fields see [`mod@ic_comp_param_1`]
839module"]
840pub type IC_COMP_PARAM_1 = crate::Reg<ic_comp_param_1::IC_COMP_PARAM_1_SPEC>;
841#[doc = "Component Parameter Register 1
842
843 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"]
844pub mod ic_comp_param_1;
845#[doc = "IC_COMP_VERSION (r) register accessor: I2C Component Version Register
846
847You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
848
849For information about available fields see [`mod@ic_comp_version`]
850module"]
851pub type IC_COMP_VERSION = crate::Reg<ic_comp_version::IC_COMP_VERSION_SPEC>;
852#[doc = "I2C Component Version Register"]
853pub mod ic_comp_version;
854#[doc = "IC_COMP_TYPE (r) register accessor: I2C Component Type Register
855
856You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
857
858For information about available fields see [`mod@ic_comp_type`]
859module"]
860pub type IC_COMP_TYPE = crate::Reg<ic_comp_type::IC_COMP_TYPE_SPEC>;
861#[doc = "I2C Component Type Register"]
862pub mod ic_comp_type;