1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 cpuid: CPUID,
5 gpio_in: GPIO_IN,
6 gpio_hi_in: GPIO_HI_IN,
7 _reserved3: [u8; 0x04],
8 gpio_out: GPIO_OUT,
9 gpio_out_set: GPIO_OUT_SET,
10 gpio_out_clr: GPIO_OUT_CLR,
11 gpio_out_xor: GPIO_OUT_XOR,
12 gpio_oe: GPIO_OE,
13 gpio_oe_set: GPIO_OE_SET,
14 gpio_oe_clr: GPIO_OE_CLR,
15 gpio_oe_xor: GPIO_OE_XOR,
16 gpio_hi_out: GPIO_HI_OUT,
17 gpio_hi_out_set: GPIO_HI_OUT_SET,
18 gpio_hi_out_clr: GPIO_HI_OUT_CLR,
19 gpio_hi_out_xor: GPIO_HI_OUT_XOR,
20 gpio_hi_oe: GPIO_HI_OE,
21 gpio_hi_oe_set: GPIO_HI_OE_SET,
22 gpio_hi_oe_clr: GPIO_HI_OE_CLR,
23 gpio_hi_oe_xor: GPIO_HI_OE_XOR,
24 fifo_st: FIFO_ST,
25 fifo_wr: FIFO_WR,
26 fifo_rd: FIFO_RD,
27 spinlock_st: SPINLOCK_ST,
28 div_udividend: DIV_UDIVIDEND,
29 div_udivisor: DIV_UDIVISOR,
30 div_sdividend: DIV_SDIVIDEND,
31 div_sdivisor: DIV_SDIVISOR,
32 div_quotient: DIV_QUOTIENT,
33 div_remainder: DIV_REMAINDER,
34 div_csr: DIV_CSR,
35 _reserved30: [u8; 0x04],
36 interp0_accum0: INTERP0_ACCUM0,
37 interp0_accum1: INTERP0_ACCUM1,
38 interp0_base0: INTERP0_BASE0,
39 interp0_base1: INTERP0_BASE1,
40 interp0_base2: INTERP0_BASE2,
41 interp0_pop_lane0: INTERP0_POP_LANE0,
42 interp0_pop_lane1: INTERP0_POP_LANE1,
43 interp0_pop_full: INTERP0_POP_FULL,
44 interp0_peek_lane0: INTERP0_PEEK_LANE0,
45 interp0_peek_lane1: INTERP0_PEEK_LANE1,
46 interp0_peek_full: INTERP0_PEEK_FULL,
47 interp0_ctrl_lane0: INTERP0_CTRL_LANE0,
48 interp0_ctrl_lane1: INTERP0_CTRL_LANE1,
49 interp0_accum0_add: INTERP0_ACCUM0_ADD,
50 interp0_accum1_add: INTERP0_ACCUM1_ADD,
51 interp0_base_1and0: INTERP0_BASE_1AND0,
52 interp1_accum0: INTERP1_ACCUM0,
53 interp1_accum1: INTERP1_ACCUM1,
54 interp1_base0: INTERP1_BASE0,
55 interp1_base1: INTERP1_BASE1,
56 interp1_base2: INTERP1_BASE2,
57 interp1_pop_lane0: INTERP1_POP_LANE0,
58 interp1_pop_lane1: INTERP1_POP_LANE1,
59 interp1_pop_full: INTERP1_POP_FULL,
60 interp1_peek_lane0: INTERP1_PEEK_LANE0,
61 interp1_peek_lane1: INTERP1_PEEK_LANE1,
62 interp1_peek_full: INTERP1_PEEK_FULL,
63 interp1_ctrl_lane0: INTERP1_CTRL_LANE0,
64 interp1_ctrl_lane1: INTERP1_CTRL_LANE1,
65 interp1_accum0_add: INTERP1_ACCUM0_ADD,
66 interp1_accum1_add: INTERP1_ACCUM1_ADD,
67 interp1_base_1and0: INTERP1_BASE_1AND0,
68 spinlock: [SPINLOCK; 32],
69}
70impl RegisterBlock {
71 #[doc = "0x00 - Processor core identifier
72 Value is 0 when read from processor core 0, and 1 when read from processor core 1."]
73 #[inline(always)]
74 pub const fn cpuid(&self) -> &CPUID {
75 &self.cpuid
76 }
77 #[doc = "0x04 - Input value for GPIO pins"]
78 #[inline(always)]
79 pub const fn gpio_in(&self) -> &GPIO_IN {
80 &self.gpio_in
81 }
82 #[doc = "0x08 - Input value for QSPI pins"]
83 #[inline(always)]
84 pub const fn gpio_hi_in(&self) -> &GPIO_HI_IN {
85 &self.gpio_hi_in
86 }
87 #[doc = "0x10 - GPIO output value"]
88 #[inline(always)]
89 pub const fn gpio_out(&self) -> &GPIO_OUT {
90 &self.gpio_out
91 }
92 #[doc = "0x14 - GPIO output value set"]
93 #[inline(always)]
94 pub const fn gpio_out_set(&self) -> &GPIO_OUT_SET {
95 &self.gpio_out_set
96 }
97 #[doc = "0x18 - GPIO output value clear"]
98 #[inline(always)]
99 pub const fn gpio_out_clr(&self) -> &GPIO_OUT_CLR {
100 &self.gpio_out_clr
101 }
102 #[doc = "0x1c - GPIO output value XOR"]
103 #[inline(always)]
104 pub const fn gpio_out_xor(&self) -> &GPIO_OUT_XOR {
105 &self.gpio_out_xor
106 }
107 #[doc = "0x20 - GPIO output enable"]
108 #[inline(always)]
109 pub const fn gpio_oe(&self) -> &GPIO_OE {
110 &self.gpio_oe
111 }
112 #[doc = "0x24 - GPIO output enable set"]
113 #[inline(always)]
114 pub const fn gpio_oe_set(&self) -> &GPIO_OE_SET {
115 &self.gpio_oe_set
116 }
117 #[doc = "0x28 - GPIO output enable clear"]
118 #[inline(always)]
119 pub const fn gpio_oe_clr(&self) -> &GPIO_OE_CLR {
120 &self.gpio_oe_clr
121 }
122 #[doc = "0x2c - GPIO output enable XOR"]
123 #[inline(always)]
124 pub const fn gpio_oe_xor(&self) -> &GPIO_OE_XOR {
125 &self.gpio_oe_xor
126 }
127 #[doc = "0x30 - QSPI output value"]
128 #[inline(always)]
129 pub const fn gpio_hi_out(&self) -> &GPIO_HI_OUT {
130 &self.gpio_hi_out
131 }
132 #[doc = "0x34 - QSPI output value set"]
133 #[inline(always)]
134 pub const fn gpio_hi_out_set(&self) -> &GPIO_HI_OUT_SET {
135 &self.gpio_hi_out_set
136 }
137 #[doc = "0x38 - QSPI output value clear"]
138 #[inline(always)]
139 pub const fn gpio_hi_out_clr(&self) -> &GPIO_HI_OUT_CLR {
140 &self.gpio_hi_out_clr
141 }
142 #[doc = "0x3c - QSPI output value XOR"]
143 #[inline(always)]
144 pub const fn gpio_hi_out_xor(&self) -> &GPIO_HI_OUT_XOR {
145 &self.gpio_hi_out_xor
146 }
147 #[doc = "0x40 - QSPI output enable"]
148 #[inline(always)]
149 pub const fn gpio_hi_oe(&self) -> &GPIO_HI_OE {
150 &self.gpio_hi_oe
151 }
152 #[doc = "0x44 - QSPI output enable set"]
153 #[inline(always)]
154 pub const fn gpio_hi_oe_set(&self) -> &GPIO_HI_OE_SET {
155 &self.gpio_hi_oe_set
156 }
157 #[doc = "0x48 - QSPI output enable clear"]
158 #[inline(always)]
159 pub const fn gpio_hi_oe_clr(&self) -> &GPIO_HI_OE_CLR {
160 &self.gpio_hi_oe_clr
161 }
162 #[doc = "0x4c - QSPI output enable XOR"]
163 #[inline(always)]
164 pub const fn gpio_hi_oe_xor(&self) -> &GPIO_HI_OE_XOR {
165 &self.gpio_hi_oe_xor
166 }
167 #[doc = "0x50 - Status register for inter-core FIFOs (mailboxes).
168 There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
169 Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
170 Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
171 The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."]
172 #[inline(always)]
173 pub const fn fifo_st(&self) -> &FIFO_ST {
174 &self.fifo_st
175 }
176 #[doc = "0x54 - Write access to this core's TX FIFO"]
177 #[inline(always)]
178 pub const fn fifo_wr(&self) -> &FIFO_WR {
179 &self.fifo_wr
180 }
181 #[doc = "0x58 - Read access to this core's RX FIFO"]
182 #[inline(always)]
183 pub const fn fifo_rd(&self) -> &FIFO_RD {
184 &self.fifo_rd
185 }
186 #[doc = "0x5c - Spinlock state
187 A bitmap containing the state of all 32 spinlocks (1=locked).
188 Mainly intended for debugging."]
189 #[inline(always)]
190 pub const fn spinlock_st(&self) -> &SPINLOCK_ST {
191 &self.spinlock_st
192 }
193 #[doc = "0x60 - Divider unsigned dividend
194 Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.
195 Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
196 UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
197 unsigned calculation, and the S alias starts a signed calculation."]
198 #[inline(always)]
199 pub const fn div_udividend(&self) -> &DIV_UDIVIDEND {
200 &self.div_udividend
201 }
202 #[doc = "0x64 - Divider unsigned divisor
203 Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.
204 Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
205 UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an
206 unsigned calculation, and the S alias starts a signed calculation."]
207 #[inline(always)]
208 pub const fn div_udivisor(&self) -> &DIV_UDIVISOR {
209 &self.div_udivisor
210 }
211 #[doc = "0x68 - Divider signed dividend
212 The same as UDIVIDEND, but starts a signed calculation, rather than unsigned."]
213 #[inline(always)]
214 pub const fn div_sdividend(&self) -> &DIV_SDIVIDEND {
215 &self.div_sdividend
216 }
217 #[doc = "0x6c - Divider signed divisor
218 The same as UDIVISOR, but starts a signed calculation, rather than unsigned."]
219 #[inline(always)]
220 pub const fn div_sdivisor(&self) -> &DIV_SDIVISOR {
221 &self.div_sdivisor
222 }
223 #[doc = "0x70 - Divider result quotient
224 The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.
225 For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
226 This register can be written to directly, for context save/restore purposes. This halts any
227 in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
228 Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
229 REMAINDER, QUOTIENT if CSR_DIRTY is used."]
230 #[inline(always)]
231 pub const fn div_quotient(&self) -> &DIV_QUOTIENT {
232 &self.div_quotient
233 }
234 #[doc = "0x74 - Divider result remainder
235 The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.
236 For signed calculations, REMAINDER is negative only when DIVIDEND is negative.
237 This register can be written to directly, for context save/restore purposes. This halts any
238 in-progress calculation and sets the CSR_READY and CSR_DIRTY flags."]
239 #[inline(always)]
240 pub const fn div_remainder(&self) -> &DIV_REMAINDER {
241 &self.div_remainder
242 }
243 #[doc = "0x78 - Control and status register for divider."]
244 #[inline(always)]
245 pub const fn div_csr(&self) -> &DIV_CSR {
246 &self.div_csr
247 }
248 #[doc = "0x80 - Read/write access to accumulator 0"]
249 #[inline(always)]
250 pub const fn interp0_accum0(&self) -> &INTERP0_ACCUM0 {
251 &self.interp0_accum0
252 }
253 #[doc = "0x84 - Read/write access to accumulator 1"]
254 #[inline(always)]
255 pub const fn interp0_accum1(&self) -> &INTERP0_ACCUM1 {
256 &self.interp0_accum1
257 }
258 #[doc = "0x88 - Read/write access to BASE0 register."]
259 #[inline(always)]
260 pub const fn interp0_base0(&self) -> &INTERP0_BASE0 {
261 &self.interp0_base0
262 }
263 #[doc = "0x8c - Read/write access to BASE1 register."]
264 #[inline(always)]
265 pub const fn interp0_base1(&self) -> &INTERP0_BASE1 {
266 &self.interp0_base1
267 }
268 #[doc = "0x90 - Read/write access to BASE2 register."]
269 #[inline(always)]
270 pub const fn interp0_base2(&self) -> &INTERP0_BASE2 {
271 &self.interp0_base2
272 }
273 #[doc = "0x94 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."]
274 #[inline(always)]
275 pub const fn interp0_pop_lane0(&self) -> &INTERP0_POP_LANE0 {
276 &self.interp0_pop_lane0
277 }
278 #[doc = "0x98 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."]
279 #[inline(always)]
280 pub const fn interp0_pop_lane1(&self) -> &INTERP0_POP_LANE1 {
281 &self.interp0_pop_lane1
282 }
283 #[doc = "0x9c - Read FULL result, and simultaneously write lane results to both accumulators (POP)."]
284 #[inline(always)]
285 pub const fn interp0_pop_full(&self) -> &INTERP0_POP_FULL {
286 &self.interp0_pop_full
287 }
288 #[doc = "0xa0 - Read LANE0 result, without altering any internal state (PEEK)."]
289 #[inline(always)]
290 pub const fn interp0_peek_lane0(&self) -> &INTERP0_PEEK_LANE0 {
291 &self.interp0_peek_lane0
292 }
293 #[doc = "0xa4 - Read LANE1 result, without altering any internal state (PEEK)."]
294 #[inline(always)]
295 pub const fn interp0_peek_lane1(&self) -> &INTERP0_PEEK_LANE1 {
296 &self.interp0_peek_lane1
297 }
298 #[doc = "0xa8 - Read FULL result, without altering any internal state (PEEK)."]
299 #[inline(always)]
300 pub const fn interp0_peek_full(&self) -> &INTERP0_PEEK_FULL {
301 &self.interp0_peek_full
302 }
303 #[doc = "0xac - Control register for lane 0"]
304 #[inline(always)]
305 pub const fn interp0_ctrl_lane0(&self) -> &INTERP0_CTRL_LANE0 {
306 &self.interp0_ctrl_lane0
307 }
308 #[doc = "0xb0 - Control register for lane 1"]
309 #[inline(always)]
310 pub const fn interp0_ctrl_lane1(&self) -> &INTERP0_CTRL_LANE1 {
311 &self.interp0_ctrl_lane1
312 }
313 #[doc = "0xb4 - Values written here are atomically added to ACCUM0
314 Reading yields lane 0's raw shift and mask value (BASE0 not added)."]
315 #[inline(always)]
316 pub const fn interp0_accum0_add(&self) -> &INTERP0_ACCUM0_ADD {
317 &self.interp0_accum0_add
318 }
319 #[doc = "0xb8 - Values written here are atomically added to ACCUM1
320 Reading yields lane 1's raw shift and mask value (BASE1 not added)."]
321 #[inline(always)]
322 pub const fn interp0_accum1_add(&self) -> &INTERP0_ACCUM1_ADD {
323 &self.interp0_accum1_add
324 }
325 #[doc = "0xbc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
326 Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."]
327 #[inline(always)]
328 pub const fn interp0_base_1and0(&self) -> &INTERP0_BASE_1AND0 {
329 &self.interp0_base_1and0
330 }
331 #[doc = "0xc0 - Read/write access to accumulator 0"]
332 #[inline(always)]
333 pub const fn interp1_accum0(&self) -> &INTERP1_ACCUM0 {
334 &self.interp1_accum0
335 }
336 #[doc = "0xc4 - Read/write access to accumulator 1"]
337 #[inline(always)]
338 pub const fn interp1_accum1(&self) -> &INTERP1_ACCUM1 {
339 &self.interp1_accum1
340 }
341 #[doc = "0xc8 - Read/write access to BASE0 register."]
342 #[inline(always)]
343 pub const fn interp1_base0(&self) -> &INTERP1_BASE0 {
344 &self.interp1_base0
345 }
346 #[doc = "0xcc - Read/write access to BASE1 register."]
347 #[inline(always)]
348 pub const fn interp1_base1(&self) -> &INTERP1_BASE1 {
349 &self.interp1_base1
350 }
351 #[doc = "0xd0 - Read/write access to BASE2 register."]
352 #[inline(always)]
353 pub const fn interp1_base2(&self) -> &INTERP1_BASE2 {
354 &self.interp1_base2
355 }
356 #[doc = "0xd4 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."]
357 #[inline(always)]
358 pub const fn interp1_pop_lane0(&self) -> &INTERP1_POP_LANE0 {
359 &self.interp1_pop_lane0
360 }
361 #[doc = "0xd8 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."]
362 #[inline(always)]
363 pub const fn interp1_pop_lane1(&self) -> &INTERP1_POP_LANE1 {
364 &self.interp1_pop_lane1
365 }
366 #[doc = "0xdc - Read FULL result, and simultaneously write lane results to both accumulators (POP)."]
367 #[inline(always)]
368 pub const fn interp1_pop_full(&self) -> &INTERP1_POP_FULL {
369 &self.interp1_pop_full
370 }
371 #[doc = "0xe0 - Read LANE0 result, without altering any internal state (PEEK)."]
372 #[inline(always)]
373 pub const fn interp1_peek_lane0(&self) -> &INTERP1_PEEK_LANE0 {
374 &self.interp1_peek_lane0
375 }
376 #[doc = "0xe4 - Read LANE1 result, without altering any internal state (PEEK)."]
377 #[inline(always)]
378 pub const fn interp1_peek_lane1(&self) -> &INTERP1_PEEK_LANE1 {
379 &self.interp1_peek_lane1
380 }
381 #[doc = "0xe8 - Read FULL result, without altering any internal state (PEEK)."]
382 #[inline(always)]
383 pub const fn interp1_peek_full(&self) -> &INTERP1_PEEK_FULL {
384 &self.interp1_peek_full
385 }
386 #[doc = "0xec - Control register for lane 0"]
387 #[inline(always)]
388 pub const fn interp1_ctrl_lane0(&self) -> &INTERP1_CTRL_LANE0 {
389 &self.interp1_ctrl_lane0
390 }
391 #[doc = "0xf0 - Control register for lane 1"]
392 #[inline(always)]
393 pub const fn interp1_ctrl_lane1(&self) -> &INTERP1_CTRL_LANE1 {
394 &self.interp1_ctrl_lane1
395 }
396 #[doc = "0xf4 - Values written here are atomically added to ACCUM0
397 Reading yields lane 0's raw shift and mask value (BASE0 not added)."]
398 #[inline(always)]
399 pub const fn interp1_accum0_add(&self) -> &INTERP1_ACCUM0_ADD {
400 &self.interp1_accum0_add
401 }
402 #[doc = "0xf8 - Values written here are atomically added to ACCUM1
403 Reading yields lane 1's raw shift and mask value (BASE1 not added)."]
404 #[inline(always)]
405 pub const fn interp1_accum1_add(&self) -> &INTERP1_ACCUM1_ADD {
406 &self.interp1_accum1_add
407 }
408 #[doc = "0xfc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
409 Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."]
410 #[inline(always)]
411 pub const fn interp1_base_1and0(&self) -> &INTERP1_BASE_1AND0 {
412 &self.interp1_base_1and0
413 }
414 #[doc = "0x100..0x180 - Reading from a spinlock address will:
415 - Return 0 if lock is already locked
416 - Otherwise return nonzero, and simultaneously claim the lock
417
418 Writing (any value) releases the lock.
419 If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
420 The value returned on success is 0x1 << lock number."]
421 #[inline(always)]
422 pub const fn spinlock(&self, n: usize) -> &SPINLOCK {
423 &self.spinlock[n]
424 }
425 #[doc = "Iterator for array of:"]
426 #[doc = "0x100..0x180 - Reading from a spinlock address will:
427 - Return 0 if lock is already locked
428 - Otherwise return nonzero, and simultaneously claim the lock
429
430 Writing (any value) releases the lock.
431 If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
432 The value returned on success is 0x1 << lock number."]
433 #[inline(always)]
434 pub fn spinlock_iter(&self) -> impl Iterator<Item = &SPINLOCK> {
435 self.spinlock.iter()
436 }
437}
438#[doc = "CPUID (r) register accessor: Processor core identifier
439 Value is 0 when read from processor core 0, and 1 when read from processor core 1.
440
441You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
442
443For information about available fields see [`mod@cpuid`]
444module"]
445pub type CPUID = crate::Reg<cpuid::CPUID_SPEC>;
446#[doc = "Processor core identifier
447 Value is 0 when read from processor core 0, and 1 when read from processor core 1."]
448pub mod cpuid;
449#[doc = "GPIO_IN (r) register accessor: Input value for GPIO pins
450
451You can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
452
453For information about available fields see [`mod@gpio_in`]
454module"]
455pub type GPIO_IN = crate::Reg<gpio_in::GPIO_IN_SPEC>;
456#[doc = "Input value for GPIO pins"]
457pub mod gpio_in;
458#[doc = "GPIO_HI_IN (r) register accessor: Input value for QSPI pins
459
460You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_in::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
461
462For information about available fields see [`mod@gpio_hi_in`]
463module"]
464pub type GPIO_HI_IN = crate::Reg<gpio_hi_in::GPIO_HI_IN_SPEC>;
465#[doc = "Input value for QSPI pins"]
466pub mod gpio_hi_in;
467#[doc = "GPIO_OUT (rw) register accessor: GPIO output value
468
469You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
470
471For information about available fields see [`mod@gpio_out`]
472module"]
473pub type GPIO_OUT = crate::Reg<gpio_out::GPIO_OUT_SPEC>;
474#[doc = "GPIO output value"]
475pub mod gpio_out;
476#[doc = "GPIO_OUT_SET (w) register accessor: GPIO output value set
477
478You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
479
480For information about available fields see [`mod@gpio_out_set`]
481module"]
482pub type GPIO_OUT_SET = crate::Reg<gpio_out_set::GPIO_OUT_SET_SPEC>;
483#[doc = "GPIO output value set"]
484pub mod gpio_out_set;
485#[doc = "GPIO_OUT_CLR (w) register accessor: GPIO output value clear
486
487You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
488
489For information about available fields see [`mod@gpio_out_clr`]
490module"]
491pub type GPIO_OUT_CLR = crate::Reg<gpio_out_clr::GPIO_OUT_CLR_SPEC>;
492#[doc = "GPIO output value clear"]
493pub mod gpio_out_clr;
494#[doc = "GPIO_OUT_XOR (w) register accessor: GPIO output value XOR
495
496You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
497
498For information about available fields see [`mod@gpio_out_xor`]
499module"]
500pub type GPIO_OUT_XOR = crate::Reg<gpio_out_xor::GPIO_OUT_XOR_SPEC>;
501#[doc = "GPIO output value XOR"]
502pub mod gpio_out_xor;
503#[doc = "GPIO_OE (rw) register accessor: GPIO output enable
504
505You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
506
507For information about available fields see [`mod@gpio_oe`]
508module"]
509pub type GPIO_OE = crate::Reg<gpio_oe::GPIO_OE_SPEC>;
510#[doc = "GPIO output enable"]
511pub mod gpio_oe;
512#[doc = "GPIO_OE_SET (w) register accessor: GPIO output enable set
513
514You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
515
516For information about available fields see [`mod@gpio_oe_set`]
517module"]
518pub type GPIO_OE_SET = crate::Reg<gpio_oe_set::GPIO_OE_SET_SPEC>;
519#[doc = "GPIO output enable set"]
520pub mod gpio_oe_set;
521#[doc = "GPIO_OE_CLR (w) register accessor: GPIO output enable clear
522
523You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
524
525For information about available fields see [`mod@gpio_oe_clr`]
526module"]
527pub type GPIO_OE_CLR = crate::Reg<gpio_oe_clr::GPIO_OE_CLR_SPEC>;
528#[doc = "GPIO output enable clear"]
529pub mod gpio_oe_clr;
530#[doc = "GPIO_OE_XOR (w) register accessor: GPIO output enable XOR
531
532You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
533
534For information about available fields see [`mod@gpio_oe_xor`]
535module"]
536pub type GPIO_OE_XOR = crate::Reg<gpio_oe_xor::GPIO_OE_XOR_SPEC>;
537#[doc = "GPIO output enable XOR"]
538pub mod gpio_oe_xor;
539#[doc = "GPIO_HI_OUT (rw) register accessor: QSPI output value
540
541You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
542
543For information about available fields see [`mod@gpio_hi_out`]
544module"]
545pub type GPIO_HI_OUT = crate::Reg<gpio_hi_out::GPIO_HI_OUT_SPEC>;
546#[doc = "QSPI output value"]
547pub mod gpio_hi_out;
548#[doc = "GPIO_HI_OUT_SET (w) register accessor: QSPI output value set
549
550You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
551
552For information about available fields see [`mod@gpio_hi_out_set`]
553module"]
554pub type GPIO_HI_OUT_SET = crate::Reg<gpio_hi_out_set::GPIO_HI_OUT_SET_SPEC>;
555#[doc = "QSPI output value set"]
556pub mod gpio_hi_out_set;
557#[doc = "GPIO_HI_OUT_CLR (w) register accessor: QSPI output value clear
558
559You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
560
561For information about available fields see [`mod@gpio_hi_out_clr`]
562module"]
563pub type GPIO_HI_OUT_CLR = crate::Reg<gpio_hi_out_clr::GPIO_HI_OUT_CLR_SPEC>;
564#[doc = "QSPI output value clear"]
565pub mod gpio_hi_out_clr;
566#[doc = "GPIO_HI_OUT_XOR (w) register accessor: QSPI output value XOR
567
568You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
569
570For information about available fields see [`mod@gpio_hi_out_xor`]
571module"]
572pub type GPIO_HI_OUT_XOR = crate::Reg<gpio_hi_out_xor::GPIO_HI_OUT_XOR_SPEC>;
573#[doc = "QSPI output value XOR"]
574pub mod gpio_hi_out_xor;
575#[doc = "GPIO_HI_OE (rw) register accessor: QSPI output enable
576
577You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
578
579For information about available fields see [`mod@gpio_hi_oe`]
580module"]
581pub type GPIO_HI_OE = crate::Reg<gpio_hi_oe::GPIO_HI_OE_SPEC>;
582#[doc = "QSPI output enable"]
583pub mod gpio_hi_oe;
584#[doc = "GPIO_HI_OE_SET (w) register accessor: QSPI output enable set
585
586You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
587
588For information about available fields see [`mod@gpio_hi_oe_set`]
589module"]
590pub type GPIO_HI_OE_SET = crate::Reg<gpio_hi_oe_set::GPIO_HI_OE_SET_SPEC>;
591#[doc = "QSPI output enable set"]
592pub mod gpio_hi_oe_set;
593#[doc = "GPIO_HI_OE_CLR (w) register accessor: QSPI output enable clear
594
595You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
596
597For information about available fields see [`mod@gpio_hi_oe_clr`]
598module"]
599pub type GPIO_HI_OE_CLR = crate::Reg<gpio_hi_oe_clr::GPIO_HI_OE_CLR_SPEC>;
600#[doc = "QSPI output enable clear"]
601pub mod gpio_hi_oe_clr;
602#[doc = "GPIO_HI_OE_XOR (w) register accessor: QSPI output enable XOR
603
604You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
605
606For information about available fields see [`mod@gpio_hi_oe_xor`]
607module"]
608pub type GPIO_HI_OE_XOR = crate::Reg<gpio_hi_oe_xor::GPIO_HI_OE_XOR_SPEC>;
609#[doc = "QSPI output enable XOR"]
610pub mod gpio_hi_oe_xor;
611#[doc = "FIFO_ST (rw) register accessor: Status register for inter-core FIFOs (mailboxes).
612 There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
613 Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
614 Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
615 The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
616
617You can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
618
619For information about available fields see [`mod@fifo_st`]
620module"]
621pub type FIFO_ST = crate::Reg<fifo_st::FIFO_ST_SPEC>;
622#[doc = "Status register for inter-core FIFOs (mailboxes).
623 There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
624 Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
625 Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
626 The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."]
627pub mod fifo_st;
628#[doc = "FIFO_WR (w) register accessor: Write access to this core's TX FIFO
629
630You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
631
632For information about available fields see [`mod@fifo_wr`]
633module"]
634pub type FIFO_WR = crate::Reg<fifo_wr::FIFO_WR_SPEC>;
635#[doc = "Write access to this core's TX FIFO"]
636pub mod fifo_wr;
637#[doc = "FIFO_RD (r) register accessor: Read access to this core's RX FIFO
638
639You can [`read`](crate::generic::Reg::read) this register and get [`fifo_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
640
641For information about available fields see [`mod@fifo_rd`]
642module"]
643pub type FIFO_RD = crate::Reg<fifo_rd::FIFO_RD_SPEC>;
644#[doc = "Read access to this core's RX FIFO"]
645pub mod fifo_rd;
646#[doc = "SPINLOCK_ST (r) register accessor: Spinlock state
647 A bitmap containing the state of all 32 spinlocks (1=locked).
648 Mainly intended for debugging.
649
650You can [`read`](crate::generic::Reg::read) this register and get [`spinlock_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
651
652For information about available fields see [`mod@spinlock_st`]
653module"]
654pub type SPINLOCK_ST = crate::Reg<spinlock_st::SPINLOCK_ST_SPEC>;
655#[doc = "Spinlock state
656 A bitmap containing the state of all 32 spinlocks (1=locked).
657 Mainly intended for debugging."]
658pub mod spinlock_st;
659#[doc = "DIV_UDIVIDEND (rw) register accessor: Divider unsigned dividend
660 Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.
661 Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
662 UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
663 unsigned calculation, and the S alias starts a signed calculation.
664
665You can [`read`](crate::generic::Reg::read) this register and get [`div_udividend::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udividend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
666
667For information about available fields see [`mod@div_udividend`]
668module"]
669pub type DIV_UDIVIDEND = crate::Reg<div_udividend::DIV_UDIVIDEND_SPEC>;
670#[doc = "Divider unsigned dividend
671 Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.
672 Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
673 UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
674 unsigned calculation, and the S alias starts a signed calculation."]
675pub mod div_udividend;
676#[doc = "DIV_UDIVISOR (rw) register accessor: Divider unsigned divisor
677 Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.
678 Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
679 UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an
680 unsigned calculation, and the S alias starts a signed calculation.
681
682You can [`read`](crate::generic::Reg::read) this register and get [`div_udivisor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udivisor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
683
684For information about available fields see [`mod@div_udivisor`]
685module"]
686pub type DIV_UDIVISOR = crate::Reg<div_udivisor::DIV_UDIVISOR_SPEC>;
687#[doc = "Divider unsigned divisor
688 Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.
689 Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
690 UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an
691 unsigned calculation, and the S alias starts a signed calculation."]
692pub mod div_udivisor;
693#[doc = "DIV_SDIVIDEND (rw) register accessor: Divider signed dividend
694 The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
695
696You can [`read`](crate::generic::Reg::read) this register and get [`div_sdividend::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdividend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
697
698For information about available fields see [`mod@div_sdividend`]
699module"]
700pub type DIV_SDIVIDEND = crate::Reg<div_sdividend::DIV_SDIVIDEND_SPEC>;
701#[doc = "Divider signed dividend
702 The same as UDIVIDEND, but starts a signed calculation, rather than unsigned."]
703pub mod div_sdividend;
704#[doc = "DIV_SDIVISOR (rw) register accessor: Divider signed divisor
705 The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
706
707You can [`read`](crate::generic::Reg::read) this register and get [`div_sdivisor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdivisor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
708
709For information about available fields see [`mod@div_sdivisor`]
710module"]
711pub type DIV_SDIVISOR = crate::Reg<div_sdivisor::DIV_SDIVISOR_SPEC>;
712#[doc = "Divider signed divisor
713 The same as UDIVISOR, but starts a signed calculation, rather than unsigned."]
714pub mod div_sdivisor;
715#[doc = "DIV_QUOTIENT (rw) register accessor: Divider result quotient
716 The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.
717 For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
718 This register can be written to directly, for context save/restore purposes. This halts any
719 in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
720 Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
721 REMAINDER, QUOTIENT if CSR_DIRTY is used.
722
723You can [`read`](crate::generic::Reg::read) this register and get [`div_quotient::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_quotient::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
724
725For information about available fields see [`mod@div_quotient`]
726module"]
727pub type DIV_QUOTIENT = crate::Reg<div_quotient::DIV_QUOTIENT_SPEC>;
728#[doc = "Divider result quotient
729 The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.
730 For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
731 This register can be written to directly, for context save/restore purposes. This halts any
732 in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
733 Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
734 REMAINDER, QUOTIENT if CSR_DIRTY is used."]
735pub mod div_quotient;
736#[doc = "DIV_REMAINDER (rw) register accessor: Divider result remainder
737 The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.
738 For signed calculations, REMAINDER is negative only when DIVIDEND is negative.
739 This register can be written to directly, for context save/restore purposes. This halts any
740 in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
741
742You can [`read`](crate::generic::Reg::read) this register and get [`div_remainder::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_remainder::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
743
744For information about available fields see [`mod@div_remainder`]
745module"]
746pub type DIV_REMAINDER = crate::Reg<div_remainder::DIV_REMAINDER_SPEC>;
747#[doc = "Divider result remainder
748 The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.
749 For signed calculations, REMAINDER is negative only when DIVIDEND is negative.
750 This register can be written to directly, for context save/restore purposes. This halts any
751 in-progress calculation and sets the CSR_READY and CSR_DIRTY flags."]
752pub mod div_remainder;
753#[doc = "DIV_CSR (r) register accessor: Control and status register for divider.
754
755You can [`read`](crate::generic::Reg::read) this register and get [`div_csr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
756
757For information about available fields see [`mod@div_csr`]
758module"]
759pub type DIV_CSR = crate::Reg<div_csr::DIV_CSR_SPEC>;
760#[doc = "Control and status register for divider."]
761pub mod div_csr;
762#[doc = "INTERP0_ACCUM0 (rw) register accessor: Read/write access to accumulator 0
763
764You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
765
766For information about available fields see [`mod@interp0_accum0`]
767module"]
768pub type INTERP0_ACCUM0 = crate::Reg<interp0_accum0::INTERP0_ACCUM0_SPEC>;
769#[doc = "Read/write access to accumulator 0"]
770pub mod interp0_accum0;
771#[doc = "INTERP0_ACCUM1 (rw) register accessor: Read/write access to accumulator 1
772
773You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
774
775For information about available fields see [`mod@interp0_accum1`]
776module"]
777pub type INTERP0_ACCUM1 = crate::Reg<interp0_accum1::INTERP0_ACCUM1_SPEC>;
778#[doc = "Read/write access to accumulator 1"]
779pub mod interp0_accum1;
780#[doc = "INTERP0_BASE0 (rw) register accessor: Read/write access to BASE0 register.
781
782You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
783
784For information about available fields see [`mod@interp0_base0`]
785module"]
786pub type INTERP0_BASE0 = crate::Reg<interp0_base0::INTERP0_BASE0_SPEC>;
787#[doc = "Read/write access to BASE0 register."]
788pub mod interp0_base0;
789#[doc = "INTERP0_BASE1 (rw) register accessor: Read/write access to BASE1 register.
790
791You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
792
793For information about available fields see [`mod@interp0_base1`]
794module"]
795pub type INTERP0_BASE1 = crate::Reg<interp0_base1::INTERP0_BASE1_SPEC>;
796#[doc = "Read/write access to BASE1 register."]
797pub mod interp0_base1;
798#[doc = "INTERP0_BASE2 (rw) register accessor: Read/write access to BASE2 register.
799
800You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
801
802For information about available fields see [`mod@interp0_base2`]
803module"]
804pub type INTERP0_BASE2 = crate::Reg<interp0_base2::INTERP0_BASE2_SPEC>;
805#[doc = "Read/write access to BASE2 register."]
806pub mod interp0_base2;
807#[doc = "INTERP0_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
808
809You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
810
811For information about available fields see [`mod@interp0_pop_lane0`]
812module"]
813pub type INTERP0_POP_LANE0 = crate::Reg<interp0_pop_lane0::INTERP0_POP_LANE0_SPEC>;
814#[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."]
815pub mod interp0_pop_lane0;
816#[doc = "INTERP0_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
817
818You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
819
820For information about available fields see [`mod@interp0_pop_lane1`]
821module"]
822pub type INTERP0_POP_LANE1 = crate::Reg<interp0_pop_lane1::INTERP0_POP_LANE1_SPEC>;
823#[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."]
824pub mod interp0_pop_lane1;
825#[doc = "INTERP0_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP).
826
827You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
828
829For information about available fields see [`mod@interp0_pop_full`]
830module"]
831pub type INTERP0_POP_FULL = crate::Reg<interp0_pop_full::INTERP0_POP_FULL_SPEC>;
832#[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."]
833pub mod interp0_pop_full;
834#[doc = "INTERP0_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK).
835
836You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
837
838For information about available fields see [`mod@interp0_peek_lane0`]
839module"]
840pub type INTERP0_PEEK_LANE0 = crate::Reg<interp0_peek_lane0::INTERP0_PEEK_LANE0_SPEC>;
841#[doc = "Read LANE0 result, without altering any internal state (PEEK)."]
842pub mod interp0_peek_lane0;
843#[doc = "INTERP0_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK).
844
845You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
846
847For information about available fields see [`mod@interp0_peek_lane1`]
848module"]
849pub type INTERP0_PEEK_LANE1 = crate::Reg<interp0_peek_lane1::INTERP0_PEEK_LANE1_SPEC>;
850#[doc = "Read LANE1 result, without altering any internal state (PEEK)."]
851pub mod interp0_peek_lane1;
852#[doc = "INTERP0_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK).
853
854You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
855
856For information about available fields see [`mod@interp0_peek_full`]
857module"]
858pub type INTERP0_PEEK_FULL = crate::Reg<interp0_peek_full::INTERP0_PEEK_FULL_SPEC>;
859#[doc = "Read FULL result, without altering any internal state (PEEK)."]
860pub mod interp0_peek_full;
861#[doc = "INTERP0_CTRL_LANE0 (rw) register accessor: Control register for lane 0
862
863You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
864
865For information about available fields see [`mod@interp0_ctrl_lane0`]
866module"]
867pub type INTERP0_CTRL_LANE0 = crate::Reg<interp0_ctrl_lane0::INTERP0_CTRL_LANE0_SPEC>;
868#[doc = "Control register for lane 0"]
869pub mod interp0_ctrl_lane0;
870#[doc = "INTERP0_CTRL_LANE1 (rw) register accessor: Control register for lane 1
871
872You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
873
874For information about available fields see [`mod@interp0_ctrl_lane1`]
875module"]
876pub type INTERP0_CTRL_LANE1 = crate::Reg<interp0_ctrl_lane1::INTERP0_CTRL_LANE1_SPEC>;
877#[doc = "Control register for lane 1"]
878pub mod interp0_ctrl_lane1;
879#[doc = "INTERP0_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0
880 Reading yields lane 0's raw shift and mask value (BASE0 not added).
881
882You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
883
884For information about available fields see [`mod@interp0_accum0_add`]
885module"]
886pub type INTERP0_ACCUM0_ADD = crate::Reg<interp0_accum0_add::INTERP0_ACCUM0_ADD_SPEC>;
887#[doc = "Values written here are atomically added to ACCUM0
888 Reading yields lane 0's raw shift and mask value (BASE0 not added)."]
889pub mod interp0_accum0_add;
890#[doc = "INTERP0_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1
891 Reading yields lane 1's raw shift and mask value (BASE1 not added).
892
893You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
894
895For information about available fields see [`mod@interp0_accum1_add`]
896module"]
897pub type INTERP0_ACCUM1_ADD = crate::Reg<interp0_accum1_add::INTERP0_ACCUM1_ADD_SPEC>;
898#[doc = "Values written here are atomically added to ACCUM1
899 Reading yields lane 1's raw shift and mask value (BASE1 not added)."]
900pub mod interp0_accum1_add;
901#[doc = "INTERP0_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
902 Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
903
904You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
905
906For information about available fields see [`mod@interp0_base_1and0`]
907module"]
908pub type INTERP0_BASE_1AND0 = crate::Reg<interp0_base_1and0::INTERP0_BASE_1AND0_SPEC>;
909#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
910 Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."]
911pub mod interp0_base_1and0;
912#[doc = "INTERP1_ACCUM0 (rw) register accessor: Read/write access to accumulator 0
913
914You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
915
916For information about available fields see [`mod@interp1_accum0`]
917module"]
918pub type INTERP1_ACCUM0 = crate::Reg<interp1_accum0::INTERP1_ACCUM0_SPEC>;
919#[doc = "Read/write access to accumulator 0"]
920pub mod interp1_accum0;
921#[doc = "INTERP1_ACCUM1 (rw) register accessor: Read/write access to accumulator 1
922
923You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
924
925For information about available fields see [`mod@interp1_accum1`]
926module"]
927pub type INTERP1_ACCUM1 = crate::Reg<interp1_accum1::INTERP1_ACCUM1_SPEC>;
928#[doc = "Read/write access to accumulator 1"]
929pub mod interp1_accum1;
930#[doc = "INTERP1_BASE0 (rw) register accessor: Read/write access to BASE0 register.
931
932You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
933
934For information about available fields see [`mod@interp1_base0`]
935module"]
936pub type INTERP1_BASE0 = crate::Reg<interp1_base0::INTERP1_BASE0_SPEC>;
937#[doc = "Read/write access to BASE0 register."]
938pub mod interp1_base0;
939#[doc = "INTERP1_BASE1 (rw) register accessor: Read/write access to BASE1 register.
940
941You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
942
943For information about available fields see [`mod@interp1_base1`]
944module"]
945pub type INTERP1_BASE1 = crate::Reg<interp1_base1::INTERP1_BASE1_SPEC>;
946#[doc = "Read/write access to BASE1 register."]
947pub mod interp1_base1;
948#[doc = "INTERP1_BASE2 (rw) register accessor: Read/write access to BASE2 register.
949
950You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
951
952For information about available fields see [`mod@interp1_base2`]
953module"]
954pub type INTERP1_BASE2 = crate::Reg<interp1_base2::INTERP1_BASE2_SPEC>;
955#[doc = "Read/write access to BASE2 register."]
956pub mod interp1_base2;
957#[doc = "INTERP1_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
958
959You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
960
961For information about available fields see [`mod@interp1_pop_lane0`]
962module"]
963pub type INTERP1_POP_LANE0 = crate::Reg<interp1_pop_lane0::INTERP1_POP_LANE0_SPEC>;
964#[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."]
965pub mod interp1_pop_lane0;
966#[doc = "INTERP1_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
967
968You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
969
970For information about available fields see [`mod@interp1_pop_lane1`]
971module"]
972pub type INTERP1_POP_LANE1 = crate::Reg<interp1_pop_lane1::INTERP1_POP_LANE1_SPEC>;
973#[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."]
974pub mod interp1_pop_lane1;
975#[doc = "INTERP1_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP).
976
977You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
978
979For information about available fields see [`mod@interp1_pop_full`]
980module"]
981pub type INTERP1_POP_FULL = crate::Reg<interp1_pop_full::INTERP1_POP_FULL_SPEC>;
982#[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."]
983pub mod interp1_pop_full;
984#[doc = "INTERP1_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK).
985
986You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
987
988For information about available fields see [`mod@interp1_peek_lane0`]
989module"]
990pub type INTERP1_PEEK_LANE0 = crate::Reg<interp1_peek_lane0::INTERP1_PEEK_LANE0_SPEC>;
991#[doc = "Read LANE0 result, without altering any internal state (PEEK)."]
992pub mod interp1_peek_lane0;
993#[doc = "INTERP1_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK).
994
995You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
996
997For information about available fields see [`mod@interp1_peek_lane1`]
998module"]
999pub type INTERP1_PEEK_LANE1 = crate::Reg<interp1_peek_lane1::INTERP1_PEEK_LANE1_SPEC>;
1000#[doc = "Read LANE1 result, without altering any internal state (PEEK)."]
1001pub mod interp1_peek_lane1;
1002#[doc = "INTERP1_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK).
1003
1004You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1005
1006For information about available fields see [`mod@interp1_peek_full`]
1007module"]
1008pub type INTERP1_PEEK_FULL = crate::Reg<interp1_peek_full::INTERP1_PEEK_FULL_SPEC>;
1009#[doc = "Read FULL result, without altering any internal state (PEEK)."]
1010pub mod interp1_peek_full;
1011#[doc = "INTERP1_CTRL_LANE0 (rw) register accessor: Control register for lane 0
1012
1013You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1014
1015For information about available fields see [`mod@interp1_ctrl_lane0`]
1016module"]
1017pub type INTERP1_CTRL_LANE0 = crate::Reg<interp1_ctrl_lane0::INTERP1_CTRL_LANE0_SPEC>;
1018#[doc = "Control register for lane 0"]
1019pub mod interp1_ctrl_lane0;
1020#[doc = "INTERP1_CTRL_LANE1 (rw) register accessor: Control register for lane 1
1021
1022You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1023
1024For information about available fields see [`mod@interp1_ctrl_lane1`]
1025module"]
1026pub type INTERP1_CTRL_LANE1 = crate::Reg<interp1_ctrl_lane1::INTERP1_CTRL_LANE1_SPEC>;
1027#[doc = "Control register for lane 1"]
1028pub mod interp1_ctrl_lane1;
1029#[doc = "INTERP1_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0
1030 Reading yields lane 0's raw shift and mask value (BASE0 not added).
1031
1032You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1033
1034For information about available fields see [`mod@interp1_accum0_add`]
1035module"]
1036pub type INTERP1_ACCUM0_ADD = crate::Reg<interp1_accum0_add::INTERP1_ACCUM0_ADD_SPEC>;
1037#[doc = "Values written here are atomically added to ACCUM0
1038 Reading yields lane 0's raw shift and mask value (BASE0 not added)."]
1039pub mod interp1_accum0_add;
1040#[doc = "INTERP1_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1
1041 Reading yields lane 1's raw shift and mask value (BASE1 not added).
1042
1043You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1044
1045For information about available fields see [`mod@interp1_accum1_add`]
1046module"]
1047pub type INTERP1_ACCUM1_ADD = crate::Reg<interp1_accum1_add::INTERP1_ACCUM1_ADD_SPEC>;
1048#[doc = "Values written here are atomically added to ACCUM1
1049 Reading yields lane 1's raw shift and mask value (BASE1 not added)."]
1050pub mod interp1_accum1_add;
1051#[doc = "INTERP1_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
1052 Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
1053
1054You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1055
1056For information about available fields see [`mod@interp1_base_1and0`]
1057module"]
1058pub type INTERP1_BASE_1AND0 = crate::Reg<interp1_base_1and0::INTERP1_BASE_1AND0_SPEC>;
1059#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
1060 Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."]
1061pub mod interp1_base_1and0;
1062#[doc = "SPINLOCK (rw) register accessor: Reading from a spinlock address will:
1063 - Return 0 if lock is already locked
1064 - Otherwise return nonzero, and simultaneously claim the lock
1065
1066 Writing (any value) releases the lock.
1067 If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
1068 The value returned on success is 0x1 << lock number.
1069
1070You can [`read`](crate::generic::Reg::read) this register and get [`spinlock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1071
1072For information about available fields see [`mod@spinlock`]
1073module"]
1074pub type SPINLOCK = crate::Reg<spinlock::SPINLOCK_SPEC>;
1075#[doc = "Reading from a spinlock address will:
1076 - Return 0 if lock is already locked
1077 - Otherwise return nonzero, and simultaneously claim the lock
1078
1079 Writing (any value) releases the lock.
1080 If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
1081 The value returned on success is 0x1 << lock number."]
1082pub mod spinlock;