rp2040_pac/watchdog/
ctrl.rs

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1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `TIME` reader - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered"]
6pub type TIME_R = crate::FieldReader<u32>;
7#[doc = "Field `PAUSE_JTAG` reader - Pause the watchdog timer when JTAG is accessing the bus fabric"]
8pub type PAUSE_JTAG_R = crate::BitReader;
9#[doc = "Field `PAUSE_JTAG` writer - Pause the watchdog timer when JTAG is accessing the bus fabric"]
10pub type PAUSE_JTAG_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `PAUSE_DBG0` reader - Pause the watchdog timer when processor 0 is in debug mode"]
12pub type PAUSE_DBG0_R = crate::BitReader;
13#[doc = "Field `PAUSE_DBG0` writer - Pause the watchdog timer when processor 0 is in debug mode"]
14pub type PAUSE_DBG0_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `PAUSE_DBG1` reader - Pause the watchdog timer when processor 1 is in debug mode"]
16pub type PAUSE_DBG1_R = crate::BitReader;
17#[doc = "Field `PAUSE_DBG1` writer - Pause the watchdog timer when processor 1 is in debug mode"]
18pub type PAUSE_DBG1_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `ENABLE` reader - When not enabled the watchdog timer is paused"]
20pub type ENABLE_R = crate::BitReader;
21#[doc = "Field `ENABLE` writer - When not enabled the watchdog timer is paused"]
22pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `TRIGGER` reader - Trigger a watchdog reset"]
24pub type TRIGGER_R = crate::BitReader;
25#[doc = "Field `TRIGGER` writer - Trigger a watchdog reset"]
26pub type TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
27impl R {
28    #[doc = "Bits 0:23 - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered"]
29    #[inline(always)]
30    pub fn time(&self) -> TIME_R {
31        TIME_R::new(self.bits & 0x00ff_ffff)
32    }
33    #[doc = "Bit 24 - Pause the watchdog timer when JTAG is accessing the bus fabric"]
34    #[inline(always)]
35    pub fn pause_jtag(&self) -> PAUSE_JTAG_R {
36        PAUSE_JTAG_R::new(((self.bits >> 24) & 1) != 0)
37    }
38    #[doc = "Bit 25 - Pause the watchdog timer when processor 0 is in debug mode"]
39    #[inline(always)]
40    pub fn pause_dbg0(&self) -> PAUSE_DBG0_R {
41        PAUSE_DBG0_R::new(((self.bits >> 25) & 1) != 0)
42    }
43    #[doc = "Bit 26 - Pause the watchdog timer when processor 1 is in debug mode"]
44    #[inline(always)]
45    pub fn pause_dbg1(&self) -> PAUSE_DBG1_R {
46        PAUSE_DBG1_R::new(((self.bits >> 26) & 1) != 0)
47    }
48    #[doc = "Bit 30 - When not enabled the watchdog timer is paused"]
49    #[inline(always)]
50    pub fn enable(&self) -> ENABLE_R {
51        ENABLE_R::new(((self.bits >> 30) & 1) != 0)
52    }
53    #[doc = "Bit 31 - Trigger a watchdog reset"]
54    #[inline(always)]
55    pub fn trigger(&self) -> TRIGGER_R {
56        TRIGGER_R::new(((self.bits >> 31) & 1) != 0)
57    }
58}
59impl W {
60    #[doc = "Bit 24 - Pause the watchdog timer when JTAG is accessing the bus fabric"]
61    #[inline(always)]
62    #[must_use]
63    pub fn pause_jtag(&mut self) -> PAUSE_JTAG_W<CTRL_SPEC> {
64        PAUSE_JTAG_W::new(self, 24)
65    }
66    #[doc = "Bit 25 - Pause the watchdog timer when processor 0 is in debug mode"]
67    #[inline(always)]
68    #[must_use]
69    pub fn pause_dbg0(&mut self) -> PAUSE_DBG0_W<CTRL_SPEC> {
70        PAUSE_DBG0_W::new(self, 25)
71    }
72    #[doc = "Bit 26 - Pause the watchdog timer when processor 1 is in debug mode"]
73    #[inline(always)]
74    #[must_use]
75    pub fn pause_dbg1(&mut self) -> PAUSE_DBG1_W<CTRL_SPEC> {
76        PAUSE_DBG1_W::new(self, 26)
77    }
78    #[doc = "Bit 30 - When not enabled the watchdog timer is paused"]
79    #[inline(always)]
80    #[must_use]
81    pub fn enable(&mut self) -> ENABLE_W<CTRL_SPEC> {
82        ENABLE_W::new(self, 30)
83    }
84    #[doc = "Bit 31 - Trigger a watchdog reset"]
85    #[inline(always)]
86    #[must_use]
87    pub fn trigger(&mut self) -> TRIGGER_W<CTRL_SPEC> {
88        TRIGGER_W::new(self, 31)
89    }
90    #[doc = r" Writes raw bits to the register."]
91    #[doc = r""]
92    #[doc = r" # Safety"]
93    #[doc = r""]
94    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
95    #[inline(always)]
96    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
97        self.bits = bits;
98        self
99    }
100}
101#[doc = "Watchdog control  
102 The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.  
103 The watchdog can be triggered in software.  
104
105You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
106pub struct CTRL_SPEC;
107impl crate::RegisterSpec for CTRL_SPEC {
108    type Ux = u32;
109}
110#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
111impl crate::Readable for CTRL_SPEC {}
112#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
113impl crate::Writable for CTRL_SPEC {
114    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
115    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
116}
117#[doc = "`reset()` method sets CTRL to value 0x0700_0000"]
118impl crate::Resettable for CTRL_SPEC {
119    const RESET_VALUE: u32 = 0x0700_0000;
120}
rp2040_pac/watchdog/ctrl.rs

rp2040_pac/watchdog/
ctrl.rs
