rp2040_pac/pll_sys/
cs.rs

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1#[doc = "Register `CS` reader"]
2pub type R = crate::R<CS_SPEC>;
3#[doc = "Register `CS` writer"]
4pub type W = crate::W<CS_SPEC>;
5#[doc = "Field `REFDIV` reader - Divides the PLL input reference clock.  
6 Behaviour is undefined for div=0.  
7 PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."]
8pub type REFDIV_R = crate::FieldReader;
9#[doc = "Field `REFDIV` writer - Divides the PLL input reference clock.  
10 Behaviour is undefined for div=0.  
11 PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."]
12pub type REFDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `BYPASS` reader - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."]
14pub type BYPASS_R = crate::BitReader;
15#[doc = "Field `BYPASS` writer - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."]
16pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `LOCK` reader - PLL is locked"]
18pub type LOCK_R = crate::BitReader;
19impl R {
20    #[doc = "Bits 0:5 - Divides the PLL input reference clock.  
21 Behaviour is undefined for div=0.  
22 PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."]
23    #[inline(always)]
24    pub fn refdiv(&self) -> REFDIV_R {
25        REFDIV_R::new((self.bits & 0x3f) as u8)
26    }
27    #[doc = "Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."]
28    #[inline(always)]
29    pub fn bypass(&self) -> BYPASS_R {
30        BYPASS_R::new(((self.bits >> 8) & 1) != 0)
31    }
32    #[doc = "Bit 31 - PLL is locked"]
33    #[inline(always)]
34    pub fn lock(&self) -> LOCK_R {
35        LOCK_R::new(((self.bits >> 31) & 1) != 0)
36    }
37}
38impl W {
39    #[doc = "Bits 0:5 - Divides the PLL input reference clock.  
40 Behaviour is undefined for div=0.  
41 PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."]
42    #[inline(always)]
43    #[must_use]
44    pub fn refdiv(&mut self) -> REFDIV_W<CS_SPEC> {
45        REFDIV_W::new(self, 0)
46    }
47    #[doc = "Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."]
48    #[inline(always)]
49    #[must_use]
50    pub fn bypass(&mut self) -> BYPASS_W<CS_SPEC> {
51        BYPASS_W::new(self, 8)
52    }
53    #[doc = r" Writes raw bits to the register."]
54    #[doc = r""]
55    #[doc = r" # Safety"]
56    #[doc = r""]
57    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
58    #[inline(always)]
59    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
60        self.bits = bits;
61        self
62    }
63}
64#[doc = "Control and Status  
65 GENERAL CONSTRAINTS:  
66 Reference clock frequency min=5MHz, max=800MHz  
67 Feedback divider min=16, max=320  
68 VCO frequency min=750MHz, max=1600MHz  
69
70You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
71pub struct CS_SPEC;
72impl crate::RegisterSpec for CS_SPEC {
73    type Ux = u32;
74}
75#[doc = "`read()` method returns [`cs::R`](R) reader structure"]
76impl crate::Readable for CS_SPEC {}
77#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"]
78impl crate::Writable for CS_SPEC {
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
81}
82#[doc = "`reset()` method sets CS to value 0x01"]
83impl crate::Resettable for CS_SPEC {
84    const RESET_VALUE: u32 = 0x01;
85}
rp2040_pac/pll_sys/cs.rs

rp2040_pac/pll_sys/
cs.rs
