1#[doc = "Register `UARTCR` reader"]
2pub type R = crate::R<UARTCR_SPEC>;
3#[doc = "Register `UARTCR` writer"]
4pub type W = crate::W<UARTCR_SPEC>;
5#[doc = "Field `UARTEN` reader - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."]
6pub type UARTEN_R = crate::BitReader;
7#[doc = "Field `UARTEN` writer - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."]
8pub type UARTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SIREN` reader - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."]
10pub type SIREN_R = crate::BitReader;
11#[doc = "Field `SIREN` writer - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."]
12pub type SIREN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SIRLP` reader - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
14pub type SIRLP_R = crate::BitReader;
15#[doc = "Field `SIRLP` writer - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
16pub type SIRLP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `LBE` reader - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
18pub type LBE_R = crate::BitReader;
19#[doc = "Field `LBE` writer - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
20pub type LBE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TXE` reader - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
22pub type TXE_R = crate::BitReader;
23#[doc = "Field `TXE` writer - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
24pub type TXE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RXE` reader - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
26pub type RXE_R = crate::BitReader;
27#[doc = "Field `RXE` writer - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
28pub type RXE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DTR` reader - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."]
30pub type DTR_R = crate::BitReader;
31#[doc = "Field `DTR` writer - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."]
32pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RTS` reader - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
34pub type RTS_R = crate::BitReader;
35#[doc = "Field `RTS` writer - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
36pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `OUT1` reader - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
38pub type OUT1_R = crate::BitReader;
39#[doc = "Field `OUT1` writer - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
40pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `OUT2` reader - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
42pub type OUT2_R = crate::BitReader;
43#[doc = "Field `OUT2` writer - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
44pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `RTSEN` reader - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
46pub type RTSEN_R = crate::BitReader;
47#[doc = "Field `RTSEN` writer - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
48pub type RTSEN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CTSEN` reader - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
50pub type CTSEN_R = crate::BitReader;
51#[doc = "Field `CTSEN` writer - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
52pub type CTSEN_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bit 0 - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."]
55 #[inline(always)]
56 pub fn uarten(&self) -> UARTEN_R {
57 UARTEN_R::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."]
60 #[inline(always)]
61 pub fn siren(&self) -> SIREN_R {
62 SIREN_R::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
65 #[inline(always)]
66 pub fn sirlp(&self) -> SIRLP_R {
67 SIRLP_R::new(((self.bits >> 2) & 1) != 0)
68 }
69 #[doc = "Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
70 #[inline(always)]
71 pub fn lbe(&self) -> LBE_R {
72 LBE_R::new(((self.bits >> 7) & 1) != 0)
73 }
74 #[doc = "Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
75 #[inline(always)]
76 pub fn txe(&self) -> TXE_R {
77 TXE_R::new(((self.bits >> 8) & 1) != 0)
78 }
79 #[doc = "Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
80 #[inline(always)]
81 pub fn rxe(&self) -> RXE_R {
82 RXE_R::new(((self.bits >> 9) & 1) != 0)
83 }
84 #[doc = "Bit 10 - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."]
85 #[inline(always)]
86 pub fn dtr(&self) -> DTR_R {
87 DTR_R::new(((self.bits >> 10) & 1) != 0)
88 }
89 #[doc = "Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
90 #[inline(always)]
91 pub fn rts(&self) -> RTS_R {
92 RTS_R::new(((self.bits >> 11) & 1) != 0)
93 }
94 #[doc = "Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
95 #[inline(always)]
96 pub fn out1(&self) -> OUT1_R {
97 OUT1_R::new(((self.bits >> 12) & 1) != 0)
98 }
99 #[doc = "Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
100 #[inline(always)]
101 pub fn out2(&self) -> OUT2_R {
102 OUT2_R::new(((self.bits >> 13) & 1) != 0)
103 }
104 #[doc = "Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
105 #[inline(always)]
106 pub fn rtsen(&self) -> RTSEN_R {
107 RTSEN_R::new(((self.bits >> 14) & 1) != 0)
108 }
109 #[doc = "Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
110 #[inline(always)]
111 pub fn ctsen(&self) -> CTSEN_R {
112 CTSEN_R::new(((self.bits >> 15) & 1) != 0)
113 }
114}
115impl W {
116 #[doc = "Bit 0 - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."]
117 #[inline(always)]
118 #[must_use]
119 pub fn uarten(&mut self) -> UARTEN_W<UARTCR_SPEC> {
120 UARTEN_W::new(self, 0)
121 }
122 #[doc = "Bit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."]
123 #[inline(always)]
124 #[must_use]
125 pub fn siren(&mut self) -> SIREN_W<UARTCR_SPEC> {
126 SIREN_W::new(self, 1)
127 }
128 #[doc = "Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
129 #[inline(always)]
130 #[must_use]
131 pub fn sirlp(&mut self) -> SIRLP_W<UARTCR_SPEC> {
132 SIRLP_W::new(self, 2)
133 }
134 #[doc = "Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
135 #[inline(always)]
136 #[must_use]
137 pub fn lbe(&mut self) -> LBE_W<UARTCR_SPEC> {
138 LBE_W::new(self, 7)
139 }
140 #[doc = "Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
141 #[inline(always)]
142 #[must_use]
143 pub fn txe(&mut self) -> TXE_W<UARTCR_SPEC> {
144 TXE_W::new(self, 8)
145 }
146 #[doc = "Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
147 #[inline(always)]
148 #[must_use]
149 pub fn rxe(&mut self) -> RXE_W<UARTCR_SPEC> {
150 RXE_W::new(self, 9)
151 }
152 #[doc = "Bit 10 - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."]
153 #[inline(always)]
154 #[must_use]
155 pub fn dtr(&mut self) -> DTR_W<UARTCR_SPEC> {
156 DTR_W::new(self, 10)
157 }
158 #[doc = "Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
159 #[inline(always)]
160 #[must_use]
161 pub fn rts(&mut self) -> RTS_W<UARTCR_SPEC> {
162 RTS_W::new(self, 11)
163 }
164 #[doc = "Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
165 #[inline(always)]
166 #[must_use]
167 pub fn out1(&mut self) -> OUT1_W<UARTCR_SPEC> {
168 OUT1_W::new(self, 12)
169 }
170 #[doc = "Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
171 #[inline(always)]
172 #[must_use]
173 pub fn out2(&mut self) -> OUT2_W<UARTCR_SPEC> {
174 OUT2_W::new(self, 13)
175 }
176 #[doc = "Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
177 #[inline(always)]
178 #[must_use]
179 pub fn rtsen(&mut self) -> RTSEN_W<UARTCR_SPEC> {
180 RTSEN_W::new(self, 14)
181 }
182 #[doc = "Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
183 #[inline(always)]
184 #[must_use]
185 pub fn ctsen(&mut self) -> CTSEN_W<UARTCR_SPEC> {
186 CTSEN_W::new(self, 15)
187 }
188 #[doc = r" Writes raw bits to the register."]
189 #[doc = r""]
190 #[doc = r" # Safety"]
191 #[doc = r""]
192 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
193 #[inline(always)]
194 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
195 self.bits = bits;
196 self
197 }
198}
199#[doc = "Control Register, UARTCR
200
201You can [`read`](crate::generic::Reg::read) this register and get [`uartcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
202pub struct UARTCR_SPEC;
203impl crate::RegisterSpec for UARTCR_SPEC {
204 type Ux = u32;
205}
206#[doc = "`read()` method returns [`uartcr::R`](R) reader structure"]
207impl crate::Readable for UARTCR_SPEC {}
208#[doc = "`write(|w| ..)` method takes [`uartcr::W`](W) writer structure"]
209impl crate::Writable for UARTCR_SPEC {
210 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
211 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
212}
213#[doc = "`reset()` method sets UARTCR to value 0x0300"]
214impl crate::Resettable for UARTCR_SPEC {
215 const RESET_VALUE: u32 = 0x0300;
216}