rp2040_pac/clocks/
fc0_src.rs

Help
1#[doc = "Register `FC0_SRC` reader"]
2pub type R = crate::R<FC0_SRC_SPEC>;
3#[doc = "Register `FC0_SRC` writer"]
4pub type W = crate::W<FC0_SRC_SPEC>;
5#[doc = "Field `FC0_SRC` reader - "]
6pub type FC0_SRC_R = crate::FieldReader<FC0_SRC_A>;
7#[doc = "  
8
9Value on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum FC0_SRC_A {
13    #[doc = "0: `0`"]
14    NULL = 0,
15    #[doc = "1: `1`"]
16    PLL_SYS_CLKSRC_PRIMARY = 1,
17    #[doc = "2: `10`"]
18    PLL_USB_CLKSRC_PRIMARY = 2,
19    #[doc = "3: `11`"]
20    ROSC_CLKSRC = 3,
21    #[doc = "4: `100`"]
22    ROSC_CLKSRC_PH = 4,
23    #[doc = "5: `101`"]
24    XOSC_CLKSRC = 5,
25    #[doc = "6: `110`"]
26    CLKSRC_GPIN0 = 6,
27    #[doc = "7: `111`"]
28    CLKSRC_GPIN1 = 7,
29    #[doc = "8: `1000`"]
30    CLK_REF = 8,
31    #[doc = "9: `1001`"]
32    CLK_SYS = 9,
33    #[doc = "10: `1010`"]
34    CLK_PERI = 10,
35    #[doc = "11: `1011`"]
36    CLK_USB = 11,
37    #[doc = "12: `1100`"]
38    CLK_ADC = 12,
39    #[doc = "13: `1101`"]
40    CLK_RTC = 13,
41}
42impl From<FC0_SRC_A> for u8 {
43    #[inline(always)]
44    fn from(variant: FC0_SRC_A) -> Self {
45        variant as _
46    }
47}
48impl crate::FieldSpec for FC0_SRC_A {
49    type Ux = u8;
50}
51impl FC0_SRC_R {
52    #[doc = "Get enumerated values variant"]
53    #[inline(always)]
54    pub const fn variant(&self) -> Option<FC0_SRC_A> {
55        match self.bits {
56            0 => Some(FC0_SRC_A::NULL),
57            1 => Some(FC0_SRC_A::PLL_SYS_CLKSRC_PRIMARY),
58            2 => Some(FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY),
59            3 => Some(FC0_SRC_A::ROSC_CLKSRC),
60            4 => Some(FC0_SRC_A::ROSC_CLKSRC_PH),
61            5 => Some(FC0_SRC_A::XOSC_CLKSRC),
62            6 => Some(FC0_SRC_A::CLKSRC_GPIN0),
63            7 => Some(FC0_SRC_A::CLKSRC_GPIN1),
64            8 => Some(FC0_SRC_A::CLK_REF),
65            9 => Some(FC0_SRC_A::CLK_SYS),
66            10 => Some(FC0_SRC_A::CLK_PERI),
67            11 => Some(FC0_SRC_A::CLK_USB),
68            12 => Some(FC0_SRC_A::CLK_ADC),
69            13 => Some(FC0_SRC_A::CLK_RTC),
70            _ => None,
71        }
72    }
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn is_null(&self) -> bool {
76        *self == FC0_SRC_A::NULL
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn is_pll_sys_clksrc_primary(&self) -> bool {
81        *self == FC0_SRC_A::PLL_SYS_CLKSRC_PRIMARY
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn is_pll_usb_clksrc_primary(&self) -> bool {
86        *self == FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn is_rosc_clksrc(&self) -> bool {
91        *self == FC0_SRC_A::ROSC_CLKSRC
92    }
93    #[doc = "`100`"]
94    #[inline(always)]
95    pub fn is_rosc_clksrc_ph(&self) -> bool {
96        *self == FC0_SRC_A::ROSC_CLKSRC_PH
97    }
98    #[doc = "`101`"]
99    #[inline(always)]
100    pub fn is_xosc_clksrc(&self) -> bool {
101        *self == FC0_SRC_A::XOSC_CLKSRC
102    }
103    #[doc = "`110`"]
104    #[inline(always)]
105    pub fn is_clksrc_gpin0(&self) -> bool {
106        *self == FC0_SRC_A::CLKSRC_GPIN0
107    }
108    #[doc = "`111`"]
109    #[inline(always)]
110    pub fn is_clksrc_gpin1(&self) -> bool {
111        *self == FC0_SRC_A::CLKSRC_GPIN1
112    }
113    #[doc = "`1000`"]
114    #[inline(always)]
115    pub fn is_clk_ref(&self) -> bool {
116        *self == FC0_SRC_A::CLK_REF
117    }
118    #[doc = "`1001`"]
119    #[inline(always)]
120    pub fn is_clk_sys(&self) -> bool {
121        *self == FC0_SRC_A::CLK_SYS
122    }
123    #[doc = "`1010`"]
124    #[inline(always)]
125    pub fn is_clk_peri(&self) -> bool {
126        *self == FC0_SRC_A::CLK_PERI
127    }
128    #[doc = "`1011`"]
129    #[inline(always)]
130    pub fn is_clk_usb(&self) -> bool {
131        *self == FC0_SRC_A::CLK_USB
132    }
133    #[doc = "`1100`"]
134    #[inline(always)]
135    pub fn is_clk_adc(&self) -> bool {
136        *self == FC0_SRC_A::CLK_ADC
137    }
138    #[doc = "`1101`"]
139    #[inline(always)]
140    pub fn is_clk_rtc(&self) -> bool {
141        *self == FC0_SRC_A::CLK_RTC
142    }
143}
144#[doc = "Field `FC0_SRC` writer - "]
145pub type FC0_SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 8, FC0_SRC_A>;
146impl<'a, REG> FC0_SRC_W<'a, REG>
147where
148    REG: crate::Writable + crate::RegisterSpec,
149    REG::Ux: From<u8>,
150{
151    #[doc = "`0`"]
152    #[inline(always)]
153    pub fn null(self) -> &'a mut crate::W<REG> {
154        self.variant(FC0_SRC_A::NULL)
155    }
156    #[doc = "`1`"]
157    #[inline(always)]
158    pub fn pll_sys_clksrc_primary(self) -> &'a mut crate::W<REG> {
159        self.variant(FC0_SRC_A::PLL_SYS_CLKSRC_PRIMARY)
160    }
161    #[doc = "`10`"]
162    #[inline(always)]
163    pub fn pll_usb_clksrc_primary(self) -> &'a mut crate::W<REG> {
164        self.variant(FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY)
165    }
166    #[doc = "`11`"]
167    #[inline(always)]
168    pub fn rosc_clksrc(self) -> &'a mut crate::W<REG> {
169        self.variant(FC0_SRC_A::ROSC_CLKSRC)
170    }
171    #[doc = "`100`"]
172    #[inline(always)]
173    pub fn rosc_clksrc_ph(self) -> &'a mut crate::W<REG> {
174        self.variant(FC0_SRC_A::ROSC_CLKSRC_PH)
175    }
176    #[doc = "`101`"]
177    #[inline(always)]
178    pub fn xosc_clksrc(self) -> &'a mut crate::W<REG> {
179        self.variant(FC0_SRC_A::XOSC_CLKSRC)
180    }
181    #[doc = "`110`"]
182    #[inline(always)]
183    pub fn clksrc_gpin0(self) -> &'a mut crate::W<REG> {
184        self.variant(FC0_SRC_A::CLKSRC_GPIN0)
185    }
186    #[doc = "`111`"]
187    #[inline(always)]
188    pub fn clksrc_gpin1(self) -> &'a mut crate::W<REG> {
189        self.variant(FC0_SRC_A::CLKSRC_GPIN1)
190    }
191    #[doc = "`1000`"]
192    #[inline(always)]
193    pub fn clk_ref(self) -> &'a mut crate::W<REG> {
194        self.variant(FC0_SRC_A::CLK_REF)
195    }
196    #[doc = "`1001`"]
197    #[inline(always)]
198    pub fn clk_sys(self) -> &'a mut crate::W<REG> {
199        self.variant(FC0_SRC_A::CLK_SYS)
200    }
201    #[doc = "`1010`"]
202    #[inline(always)]
203    pub fn clk_peri(self) -> &'a mut crate::W<REG> {
204        self.variant(FC0_SRC_A::CLK_PERI)
205    }
206    #[doc = "`1011`"]
207    #[inline(always)]
208    pub fn clk_usb(self) -> &'a mut crate::W<REG> {
209        self.variant(FC0_SRC_A::CLK_USB)
210    }
211    #[doc = "`1100`"]
212    #[inline(always)]
213    pub fn clk_adc(self) -> &'a mut crate::W<REG> {
214        self.variant(FC0_SRC_A::CLK_ADC)
215    }
216    #[doc = "`1101`"]
217    #[inline(always)]
218    pub fn clk_rtc(self) -> &'a mut crate::W<REG> {
219        self.variant(FC0_SRC_A::CLK_RTC)
220    }
221}
222impl R {
223    #[doc = "Bits 0:7"]
224    #[inline(always)]
225    pub fn fc0_src(&self) -> FC0_SRC_R {
226        FC0_SRC_R::new((self.bits & 0xff) as u8)
227    }
228}
229impl W {
230    #[doc = "Bits 0:7"]
231    #[inline(always)]
232    #[must_use]
233    pub fn fc0_src(&mut self) -> FC0_SRC_W<FC0_SRC_SPEC> {
234        FC0_SRC_W::new(self, 0)
235    }
236    #[doc = r" Writes raw bits to the register."]
237    #[doc = r""]
238    #[doc = r" # Safety"]
239    #[doc = r""]
240    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
241    #[inline(always)]
242    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
243        self.bits = bits;
244        self
245    }
246}
247#[doc = "Clock sent to frequency counter, set to 0 when not required  
248 Writing to this register initiates the frequency count  
249
250You can [`read`](crate::generic::Reg::read) this register and get [`fc0_src::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_src::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
251pub struct FC0_SRC_SPEC;
252impl crate::RegisterSpec for FC0_SRC_SPEC {
253    type Ux = u32;
254}
255#[doc = "`read()` method returns [`fc0_src::R`](R) reader structure"]
256impl crate::Readable for FC0_SRC_SPEC {}
257#[doc = "`write(|w| ..)` method takes [`fc0_src::W`](W) writer structure"]
258impl crate::Writable for FC0_SRC_SPEC {
259    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
260    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
261}
262#[doc = "`reset()` method sets FC0_SRC to value 0"]
263impl crate::Resettable for FC0_SRC_SPEC {
264    const RESET_VALUE: u32 = 0;
265}
rp2040_pac/clocks/fc0_src.rs

rp2040_pac/clocks/
fc0_src.rs
