rp2040_pac/uart0/
uarticr.rs
1#[doc = "Register `UARTICR` reader"]
2pub type R = crate::R<UARTICR_SPEC>;
3#[doc = "Register `UARTICR` writer"]
4pub type W = crate::W<UARTICR_SPEC>;
5#[doc = "Field `RIMIC` reader - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."]
6pub type RIMIC_R = crate::BitReader;
7#[doc = "Field `RIMIC` writer - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."]
8pub type RIMIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `CTSMIC` reader - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."]
10pub type CTSMIC_R = crate::BitReader;
11#[doc = "Field `CTSMIC` writer - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."]
12pub type CTSMIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `DCDMIC` reader - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."]
14pub type DCDMIC_R = crate::BitReader;
15#[doc = "Field `DCDMIC` writer - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."]
16pub type DCDMIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `DSRMIC` reader - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."]
18pub type DSRMIC_R = crate::BitReader;
19#[doc = "Field `DSRMIC` writer - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."]
20pub type DSRMIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `RXIC` reader - Receive interrupt clear. Clears the UARTRXINTR interrupt."]
22pub type RXIC_R = crate::BitReader;
23#[doc = "Field `RXIC` writer - Receive interrupt clear. Clears the UARTRXINTR interrupt."]
24pub type RXIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `TXIC` reader - Transmit interrupt clear. Clears the UARTTXINTR interrupt."]
26pub type TXIC_R = crate::BitReader;
27#[doc = "Field `TXIC` writer - Transmit interrupt clear. Clears the UARTTXINTR interrupt."]
28pub type TXIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `RTIC` reader - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."]
30pub type RTIC_R = crate::BitReader;
31#[doc = "Field `RTIC` writer - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."]
32pub type RTIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `FEIC` reader - Framing error interrupt clear. Clears the UARTFEINTR interrupt."]
34pub type FEIC_R = crate::BitReader;
35#[doc = "Field `FEIC` writer - Framing error interrupt clear. Clears the UARTFEINTR interrupt."]
36pub type FEIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `PEIC` reader - Parity error interrupt clear. Clears the UARTPEINTR interrupt."]
38pub type PEIC_R = crate::BitReader;
39#[doc = "Field `PEIC` writer - Parity error interrupt clear. Clears the UARTPEINTR interrupt."]
40pub type PEIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `BEIC` reader - Break error interrupt clear. Clears the UARTBEINTR interrupt."]
42pub type BEIC_R = crate::BitReader;
43#[doc = "Field `BEIC` writer - Break error interrupt clear. Clears the UARTBEINTR interrupt."]
44pub type BEIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
45#[doc = "Field `OEIC` reader - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."]
46pub type OEIC_R = crate::BitReader;
47#[doc = "Field `OEIC` writer - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."]
48pub type OEIC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
49impl R {
50 #[doc = "Bit 0 - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."]
51 #[inline(always)]
52 pub fn rimic(&self) -> RIMIC_R {
53 RIMIC_R::new((self.bits & 1) != 0)
54 }
55 #[doc = "Bit 1 - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."]
56 #[inline(always)]
57 pub fn ctsmic(&self) -> CTSMIC_R {
58 CTSMIC_R::new(((self.bits >> 1) & 1) != 0)
59 }
60 #[doc = "Bit 2 - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."]
61 #[inline(always)]
62 pub fn dcdmic(&self) -> DCDMIC_R {
63 DCDMIC_R::new(((self.bits >> 2) & 1) != 0)
64 }
65 #[doc = "Bit 3 - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."]
66 #[inline(always)]
67 pub fn dsrmic(&self) -> DSRMIC_R {
68 DSRMIC_R::new(((self.bits >> 3) & 1) != 0)
69 }
70 #[doc = "Bit 4 - Receive interrupt clear. Clears the UARTRXINTR interrupt."]
71 #[inline(always)]
72 pub fn rxic(&self) -> RXIC_R {
73 RXIC_R::new(((self.bits >> 4) & 1) != 0)
74 }
75 #[doc = "Bit 5 - Transmit interrupt clear. Clears the UARTTXINTR interrupt."]
76 #[inline(always)]
77 pub fn txic(&self) -> TXIC_R {
78 TXIC_R::new(((self.bits >> 5) & 1) != 0)
79 }
80 #[doc = "Bit 6 - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."]
81 #[inline(always)]
82 pub fn rtic(&self) -> RTIC_R {
83 RTIC_R::new(((self.bits >> 6) & 1) != 0)
84 }
85 #[doc = "Bit 7 - Framing error interrupt clear. Clears the UARTFEINTR interrupt."]
86 #[inline(always)]
87 pub fn feic(&self) -> FEIC_R {
88 FEIC_R::new(((self.bits >> 7) & 1) != 0)
89 }
90 #[doc = "Bit 8 - Parity error interrupt clear. Clears the UARTPEINTR interrupt."]
91 #[inline(always)]
92 pub fn peic(&self) -> PEIC_R {
93 PEIC_R::new(((self.bits >> 8) & 1) != 0)
94 }
95 #[doc = "Bit 9 - Break error interrupt clear. Clears the UARTBEINTR interrupt."]
96 #[inline(always)]
97 pub fn beic(&self) -> BEIC_R {
98 BEIC_R::new(((self.bits >> 9) & 1) != 0)
99 }
100 #[doc = "Bit 10 - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."]
101 #[inline(always)]
102 pub fn oeic(&self) -> OEIC_R {
103 OEIC_R::new(((self.bits >> 10) & 1) != 0)
104 }
105}
106impl W {
107 #[doc = "Bit 0 - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."]
108 #[inline(always)]
109 #[must_use]
110 pub fn rimic(&mut self) -> RIMIC_W<UARTICR_SPEC> {
111 RIMIC_W::new(self, 0)
112 }
113 #[doc = "Bit 1 - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."]
114 #[inline(always)]
115 #[must_use]
116 pub fn ctsmic(&mut self) -> CTSMIC_W<UARTICR_SPEC> {
117 CTSMIC_W::new(self, 1)
118 }
119 #[doc = "Bit 2 - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."]
120 #[inline(always)]
121 #[must_use]
122 pub fn dcdmic(&mut self) -> DCDMIC_W<UARTICR_SPEC> {
123 DCDMIC_W::new(self, 2)
124 }
125 #[doc = "Bit 3 - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."]
126 #[inline(always)]
127 #[must_use]
128 pub fn dsrmic(&mut self) -> DSRMIC_W<UARTICR_SPEC> {
129 DSRMIC_W::new(self, 3)
130 }
131 #[doc = "Bit 4 - Receive interrupt clear. Clears the UARTRXINTR interrupt."]
132 #[inline(always)]
133 #[must_use]
134 pub fn rxic(&mut self) -> RXIC_W<UARTICR_SPEC> {
135 RXIC_W::new(self, 4)
136 }
137 #[doc = "Bit 5 - Transmit interrupt clear. Clears the UARTTXINTR interrupt."]
138 #[inline(always)]
139 #[must_use]
140 pub fn txic(&mut self) -> TXIC_W<UARTICR_SPEC> {
141 TXIC_W::new(self, 5)
142 }
143 #[doc = "Bit 6 - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."]
144 #[inline(always)]
145 #[must_use]
146 pub fn rtic(&mut self) -> RTIC_W<UARTICR_SPEC> {
147 RTIC_W::new(self, 6)
148 }
149 #[doc = "Bit 7 - Framing error interrupt clear. Clears the UARTFEINTR interrupt."]
150 #[inline(always)]
151 #[must_use]
152 pub fn feic(&mut self) -> FEIC_W<UARTICR_SPEC> {
153 FEIC_W::new(self, 7)
154 }
155 #[doc = "Bit 8 - Parity error interrupt clear. Clears the UARTPEINTR interrupt."]
156 #[inline(always)]
157 #[must_use]
158 pub fn peic(&mut self) -> PEIC_W<UARTICR_SPEC> {
159 PEIC_W::new(self, 8)
160 }
161 #[doc = "Bit 9 - Break error interrupt clear. Clears the UARTBEINTR interrupt."]
162 #[inline(always)]
163 #[must_use]
164 pub fn beic(&mut self) -> BEIC_W<UARTICR_SPEC> {
165 BEIC_W::new(self, 9)
166 }
167 #[doc = "Bit 10 - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."]
168 #[inline(always)]
169 #[must_use]
170 pub fn oeic(&mut self) -> OEIC_W<UARTICR_SPEC> {
171 OEIC_W::new(self, 10)
172 }
173 #[doc = r" Writes raw bits to the register."]
174 #[doc = r""]
175 #[doc = r" # Safety"]
176 #[doc = r""]
177 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
178 #[inline(always)]
179 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
180 self.bits = bits;
181 self
182 }
183}
184#[doc = "Interrupt Clear Register, UARTICR
185
186You can [`read`](crate::generic::Reg::read) this register and get [`uarticr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uarticr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
187pub struct UARTICR_SPEC;
188impl crate::RegisterSpec for UARTICR_SPEC {
189 type Ux = u32;
190}
191#[doc = "`read()` method returns [`uarticr::R`](R) reader structure"]
192impl crate::Readable for UARTICR_SPEC {}
193#[doc = "`write(|w| ..)` method takes [`uarticr::W`](W) writer structure"]
194impl crate::Writable for UARTICR_SPEC {
195 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
196 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07ff;
197}
198#[doc = "`reset()` method sets UARTICR to value 0"]
199impl crate::Resettable for UARTICR_SPEC {
200 const RESET_VALUE: u32 = 0;
201}