rp2040_pac/xip_ssi/
dr0.rs

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1#[doc = "Register `DR0` reader"]
2pub type R = crate::R<DR0_SPEC>;
3#[doc = "Register `DR0` writer"]
4pub type W = crate::W<DR0_SPEC>;
5#[doc = "Field `DR` reader - First data register of 36"]
6pub type DR_R = crate::FieldReader<u32>;
7#[doc = "Field `DR` writer - First data register of 36"]
8pub type DR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - First data register of 36"]
11    #[inline(always)]
12    pub fn dr(&self) -> DR_R {
13        DR_R::new(self.bits)
14    }
15}
16impl W {
17    #[doc = "Bits 0:31 - First data register of 36"]
18    #[inline(always)]
19    #[must_use]
20    pub fn dr(&mut self) -> DR_W<DR0_SPEC> {
21        DR_W::new(self, 0)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "Data Register 0 (of 36)  
35
36You can [`read`](crate::generic::Reg::read) this register and get [`dr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
37pub struct DR0_SPEC;
38impl crate::RegisterSpec for DR0_SPEC {
39    type Ux = u32;
40}
41#[doc = "`read()` method returns [`dr0::R`](R) reader structure"]
42impl crate::Readable for DR0_SPEC {}
43#[doc = "`write(|w| ..)` method takes [`dr0::W`](W) writer structure"]
44impl crate::Writable for DR0_SPEC {
45    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
46    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
47}
48#[doc = "`reset()` method sets DR0 to value 0"]
49impl crate::Resettable for DR0_SPEC {
50    const RESET_VALUE: u32 = 0;
51}
rp2040_pac/xip_ssi/dr0.rs

rp2040_pac/xip_ssi/
dr0.rs
