rp2040_pac/dma/
timer2.rs

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1#[doc = "Register `TIMER2` reader"]
2pub type R = crate::R<TIMER2_SPEC>;
3#[doc = "Register `TIMER2` writer"]
4pub type W = crate::W<TIMER2_SPEC>;
5#[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
6pub type Y_R = crate::FieldReader<u16>;
7#[doc = "Field `Y` writer - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
8pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
10pub type X_R = crate::FieldReader<u16>;
11#[doc = "Field `X` writer - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
12pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13impl R {
14    #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
15    #[inline(always)]
16    pub fn y(&self) -> Y_R {
17        Y_R::new((self.bits & 0xffff) as u16)
18    }
19    #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
20    #[inline(always)]
21    pub fn x(&self) -> X_R {
22        X_R::new(((self.bits >> 16) & 0xffff) as u16)
23    }
24}
25impl W {
26    #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
27    #[inline(always)]
28    #[must_use]
29    pub fn y(&mut self) -> Y_W<TIMER2_SPEC> {
30        Y_W::new(self, 0)
31    }
32    #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
33    #[inline(always)]
34    #[must_use]
35    pub fn x(&mut self) -> X_W<TIMER2_SPEC> {
36        X_W::new(self, 16)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "Pacing (X/Y) Fractional Timer  
50 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
51
52You can [`read`](crate::generic::Reg::read) this register and get [`timer2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
53pub struct TIMER2_SPEC;
54impl crate::RegisterSpec for TIMER2_SPEC {
55    type Ux = u32;
56}
57#[doc = "`read()` method returns [`timer2::R`](R) reader structure"]
58impl crate::Readable for TIMER2_SPEC {}
59#[doc = "`write(|w| ..)` method takes [`timer2::W`](W) writer structure"]
60impl crate::Writable for TIMER2_SPEC {
61    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63}
64#[doc = "`reset()` method sets TIMER2 to value 0"]
65impl crate::Resettable for TIMER2_SPEC {
66    const RESET_VALUE: u32 = 0;
67}
rp2040_pac/dma/timer2.rs

rp2040_pac/dma/
timer2.rs
