rp2040_pac/dma/
ch.rs

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1#[doc = r"Register block"]
2#[repr(C)]
3pub struct CH {
4    ch_read_addr: CH_READ_ADDR,
5    ch_write_addr: CH_WRITE_ADDR,
6    ch_trans_count: CH_TRANS_COUNT,
7    ch_ctrl_trig: CH_CTRL_TRIG,
8    ch_al1_ctrl: CH_AL1_CTRL,
9    ch_al1_read_addr: CH_AL1_READ_ADDR,
10    ch_al1_write_addr: CH_AL1_WRITE_ADDR,
11    ch_al1_trans_count_trig: CH_AL1_TRANS_COUNT_TRIG,
12    ch_al2_ctrl: CH_AL2_CTRL,
13    ch_al2_trans_count: CH_AL2_TRANS_COUNT,
14    ch_al2_read_addr: CH_AL2_READ_ADDR,
15    ch_al2_write_addr_trig: CH_AL2_WRITE_ADDR_TRIG,
16    ch_al3_ctrl: CH_AL3_CTRL,
17    ch_al3_write_addr: CH_AL3_WRITE_ADDR,
18    ch_al3_trans_count: CH_AL3_TRANS_COUNT,
19    ch_al3_read_addr_trig: CH_AL3_READ_ADDR_TRIG,
20}
21impl CH {
22    #[doc = "0x00 - DMA Channel 0 Read Address pointer  
23 This register updates automatically each time a read completes. The current value is the next address to be read by this channel."]
24    #[inline(always)]
25    pub const fn ch_read_addr(&self) -> &CH_READ_ADDR {
26        &self.ch_read_addr
27    }
28    #[doc = "0x04 - DMA Channel 0 Write Address pointer  
29 This register updates automatically each time a write completes. The current value is the next address to be written by this channel."]
30    #[inline(always)]
31    pub const fn ch_write_addr(&self) -> &CH_WRITE_ADDR {
32        &self.ch_write_addr
33    }
34    #[doc = "0x08 - DMA Channel 0 Transfer Count  
35 Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).  
36
37 When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.  
38
39 Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.  
40
41 The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
42    #[inline(always)]
43    pub const fn ch_trans_count(&self) -> &CH_TRANS_COUNT {
44        &self.ch_trans_count
45    }
46    #[doc = "0x0c - DMA Channel 0 Control and Status"]
47    #[inline(always)]
48    pub const fn ch_ctrl_trig(&self) -> &CH_CTRL_TRIG {
49        &self.ch_ctrl_trig
50    }
51    #[doc = "0x10 - DMA Channel 0 Control and Status"]
52    #[inline(always)]
53    pub const fn ch_al1_ctrl(&self) -> &CH_AL1_CTRL {
54        &self.ch_al1_ctrl
55    }
56    #[doc = "0x14 - Alias for channel 0 READ_ADDR register"]
57    #[inline(always)]
58    pub const fn ch_al1_read_addr(&self) -> &CH_AL1_READ_ADDR {
59        &self.ch_al1_read_addr
60    }
61    #[doc = "0x18 - Alias for channel 0 WRITE_ADDR register"]
62    #[inline(always)]
63    pub const fn ch_al1_write_addr(&self) -> &CH_AL1_WRITE_ADDR {
64        &self.ch_al1_write_addr
65    }
66    #[doc = "0x1c - Alias for channel 0 TRANS_COUNT register  
67 This is a trigger register (0xc). Writing a nonzero value will  
68 reload the channel counter and start the channel."]
69    #[inline(always)]
70    pub const fn ch_al1_trans_count_trig(&self) -> &CH_AL1_TRANS_COUNT_TRIG {
71        &self.ch_al1_trans_count_trig
72    }
73    #[doc = "0x20 - DMA Channel 0 Control and Status"]
74    #[inline(always)]
75    pub const fn ch_al2_ctrl(&self) -> &CH_AL2_CTRL {
76        &self.ch_al2_ctrl
77    }
78    #[doc = "0x24 - Alias for channel 0 TRANS_COUNT register"]
79    #[inline(always)]
80    pub const fn ch_al2_trans_count(&self) -> &CH_AL2_TRANS_COUNT {
81        &self.ch_al2_trans_count
82    }
83    #[doc = "0x28 - Alias for channel 0 READ_ADDR register"]
84    #[inline(always)]
85    pub const fn ch_al2_read_addr(&self) -> &CH_AL2_READ_ADDR {
86        &self.ch_al2_read_addr
87    }
88    #[doc = "0x2c - Alias for channel 0 WRITE_ADDR register  
89 This is a trigger register (0xc). Writing a nonzero value will  
90 reload the channel counter and start the channel."]
91    #[inline(always)]
92    pub const fn ch_al2_write_addr_trig(&self) -> &CH_AL2_WRITE_ADDR_TRIG {
93        &self.ch_al2_write_addr_trig
94    }
95    #[doc = "0x30 - DMA Channel 0 Control and Status"]
96    #[inline(always)]
97    pub const fn ch_al3_ctrl(&self) -> &CH_AL3_CTRL {
98        &self.ch_al3_ctrl
99    }
100    #[doc = "0x34 - Alias for channel 0 WRITE_ADDR register"]
101    #[inline(always)]
102    pub const fn ch_al3_write_addr(&self) -> &CH_AL3_WRITE_ADDR {
103        &self.ch_al3_write_addr
104    }
105    #[doc = "0x38 - Alias for channel 0 TRANS_COUNT register"]
106    #[inline(always)]
107    pub const fn ch_al3_trans_count(&self) -> &CH_AL3_TRANS_COUNT {
108        &self.ch_al3_trans_count
109    }
110    #[doc = "0x3c - Alias for channel 0 READ_ADDR register  
111 This is a trigger register (0xc). Writing a nonzero value will  
112 reload the channel counter and start the channel."]
113    #[inline(always)]
114    pub const fn ch_al3_read_addr_trig(&self) -> &CH_AL3_READ_ADDR_TRIG {
115        &self.ch_al3_read_addr_trig
116    }
117}
118#[doc = "CH_READ_ADDR (rw) register accessor: DMA Channel 0 Read Address pointer  
119 This register updates automatically each time a read completes. The current value is the next address to be read by this channel.  
120
121You can [`read`](crate::generic::Reg::read) this register and get [`ch_read_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
122
123For information about available fields see [`mod@ch_read_addr`]
124module"]
125pub type CH_READ_ADDR = crate::Reg<ch_read_addr::CH_READ_ADDR_SPEC>;
126#[doc = "DMA Channel 0 Read Address pointer  
127 This register updates automatically each time a read completes. The current value is the next address to be read by this channel."]
128pub mod ch_read_addr;
129#[doc = "CH_WRITE_ADDR (rw) register accessor: DMA Channel 0 Write Address pointer  
130 This register updates automatically each time a write completes. The current value is the next address to be written by this channel.  
131
132You can [`read`](crate::generic::Reg::read) this register and get [`ch_write_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
133
134For information about available fields see [`mod@ch_write_addr`]
135module"]
136pub type CH_WRITE_ADDR = crate::Reg<ch_write_addr::CH_WRITE_ADDR_SPEC>;
137#[doc = "DMA Channel 0 Write Address pointer  
138 This register updates automatically each time a write completes. The current value is the next address to be written by this channel."]
139pub mod ch_write_addr;
140#[doc = "CH_TRANS_COUNT (rw) register accessor: DMA Channel 0 Transfer Count  
141 Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).  
142
143 When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.  
144
145 Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.  
146
147 The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.  
148
149You can [`read`](crate::generic::Reg::read) this register and get [`ch_trans_count::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
150
151For information about available fields see [`mod@ch_trans_count`]
152module"]
153pub type CH_TRANS_COUNT = crate::Reg<ch_trans_count::CH_TRANS_COUNT_SPEC>;
154#[doc = "DMA Channel 0 Transfer Count  
155 Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).  
156
157 When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.  
158
159 Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.  
160
161 The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
162pub mod ch_trans_count;
163#[doc = "CH_CTRL_TRIG (rw) register accessor: DMA Channel 0 Control and Status  
164
165You can [`read`](crate::generic::Reg::read) this register and get [`ch_ctrl_trig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ctrl_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
166
167For information about available fields see [`mod@ch_ctrl_trig`]
168module"]
169pub type CH_CTRL_TRIG = crate::Reg<ch_ctrl_trig::CH_CTRL_TRIG_SPEC>;
170#[doc = "DMA Channel 0 Control and Status"]
171pub mod ch_ctrl_trig;
172#[doc = "CH_AL1_CTRL (rw) register accessor: DMA Channel 0 Control and Status  
173
174You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
175
176For information about available fields see [`mod@ch_al1_ctrl`]
177module"]
178pub type CH_AL1_CTRL = crate::Reg<ch_al1_ctrl::CH_AL1_CTRL_SPEC>;
179#[doc = "DMA Channel 0 Control and Status"]
180pub mod ch_al1_ctrl;
181#[doc = "CH_AL1_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register  
182
183You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_read_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
184
185For information about available fields see [`mod@ch_al1_read_addr`]
186module"]
187pub type CH_AL1_READ_ADDR = crate::Reg<ch_al1_read_addr::CH_AL1_READ_ADDR_SPEC>;
188#[doc = "Alias for channel 0 READ_ADDR register"]
189pub mod ch_al1_read_addr;
190#[doc = "CH_AL1_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register  
191
192You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_write_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
193
194For information about available fields see [`mod@ch_al1_write_addr`]
195module"]
196pub type CH_AL1_WRITE_ADDR = crate::Reg<ch_al1_write_addr::CH_AL1_WRITE_ADDR_SPEC>;
197#[doc = "Alias for channel 0 WRITE_ADDR register"]
198pub mod ch_al1_write_addr;
199#[doc = "CH_AL1_TRANS_COUNT_TRIG (rw) register accessor: Alias for channel 0 TRANS_COUNT register  
200 This is a trigger register (0xc). Writing a nonzero value will  
201 reload the channel counter and start the channel.  
202
203You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_trans_count_trig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
204
205For information about available fields see [`mod@ch_al1_trans_count_trig`]
206module"]
207pub type CH_AL1_TRANS_COUNT_TRIG =
208    crate::Reg<ch_al1_trans_count_trig::CH_AL1_TRANS_COUNT_TRIG_SPEC>;
209#[doc = "Alias for channel 0 TRANS_COUNT register  
210 This is a trigger register (0xc). Writing a nonzero value will  
211 reload the channel counter and start the channel."]
212pub mod ch_al1_trans_count_trig;
213#[doc = "CH_AL2_CTRL (rw) register accessor: DMA Channel 0 Control and Status  
214
215You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
216
217For information about available fields see [`mod@ch_al2_ctrl`]
218module"]
219pub type CH_AL2_CTRL = crate::Reg<ch_al2_ctrl::CH_AL2_CTRL_SPEC>;
220#[doc = "DMA Channel 0 Control and Status"]
221pub mod ch_al2_ctrl;
222#[doc = "CH_AL2_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register  
223
224You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_trans_count::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
225
226For information about available fields see [`mod@ch_al2_trans_count`]
227module"]
228pub type CH_AL2_TRANS_COUNT = crate::Reg<ch_al2_trans_count::CH_AL2_TRANS_COUNT_SPEC>;
229#[doc = "Alias for channel 0 TRANS_COUNT register"]
230pub mod ch_al2_trans_count;
231#[doc = "CH_AL2_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register  
232
233You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_read_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
234
235For information about available fields see [`mod@ch_al2_read_addr`]
236module"]
237pub type CH_AL2_READ_ADDR = crate::Reg<ch_al2_read_addr::CH_AL2_READ_ADDR_SPEC>;
238#[doc = "Alias for channel 0 READ_ADDR register"]
239pub mod ch_al2_read_addr;
240#[doc = "CH_AL2_WRITE_ADDR_TRIG (rw) register accessor: Alias for channel 0 WRITE_ADDR register  
241 This is a trigger register (0xc). Writing a nonzero value will  
242 reload the channel counter and start the channel.  
243
244You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_write_addr_trig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
245
246For information about available fields see [`mod@ch_al2_write_addr_trig`]
247module"]
248pub type CH_AL2_WRITE_ADDR_TRIG = crate::Reg<ch_al2_write_addr_trig::CH_AL2_WRITE_ADDR_TRIG_SPEC>;
249#[doc = "Alias for channel 0 WRITE_ADDR register  
250 This is a trigger register (0xc). Writing a nonzero value will  
251 reload the channel counter and start the channel."]
252pub mod ch_al2_write_addr_trig;
253#[doc = "CH_AL3_CTRL (rw) register accessor: DMA Channel 0 Control and Status  
254
255You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
256
257For information about available fields see [`mod@ch_al3_ctrl`]
258module"]
259pub type CH_AL3_CTRL = crate::Reg<ch_al3_ctrl::CH_AL3_CTRL_SPEC>;
260#[doc = "DMA Channel 0 Control and Status"]
261pub mod ch_al3_ctrl;
262#[doc = "CH_AL3_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register  
263
264You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_write_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
265
266For information about available fields see [`mod@ch_al3_write_addr`]
267module"]
268pub type CH_AL3_WRITE_ADDR = crate::Reg<ch_al3_write_addr::CH_AL3_WRITE_ADDR_SPEC>;
269#[doc = "Alias for channel 0 WRITE_ADDR register"]
270pub mod ch_al3_write_addr;
271#[doc = "CH_AL3_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register  
272
273You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_trans_count::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
274
275For information about available fields see [`mod@ch_al3_trans_count`]
276module"]
277pub type CH_AL3_TRANS_COUNT = crate::Reg<ch_al3_trans_count::CH_AL3_TRANS_COUNT_SPEC>;
278#[doc = "Alias for channel 0 TRANS_COUNT register"]
279pub mod ch_al3_trans_count;
280#[doc = "CH_AL3_READ_ADDR_TRIG (rw) register accessor: Alias for channel 0 READ_ADDR register  
281 This is a trigger register (0xc). Writing a nonzero value will  
282 reload the channel counter and start the channel.  
283
284You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_read_addr_trig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
285
286For information about available fields see [`mod@ch_al3_read_addr_trig`]
287module"]
288pub type CH_AL3_READ_ADDR_TRIG = crate::Reg<ch_al3_read_addr_trig::CH_AL3_READ_ADDR_TRIG_SPEC>;
289#[doc = "Alias for channel 0 READ_ADDR register  
290 This is a trigger register (0xc). Writing a nonzero value will  
291 reload the channel counter and start the channel."]
292pub mod ch_al3_read_addr_trig;
rp2040_pac/dma/ch.rs

rp2040_pac/dma/
ch.rs
