rp2040_pac/pwm/ch/
csr.rs

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1#[doc = "Register `CSR` reader"]
2pub type R = crate::R<CSR_SPEC>;
3#[doc = "Register `CSR` writer"]
4pub type W = crate::W<CSR_SPEC>;
5#[doc = "Field `EN` reader - Enable the PWM channel."]
6pub type EN_R = crate::BitReader;
7#[doc = "Field `EN` writer - Enable the PWM channel."]
8pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PH_CORRECT` reader - 1: Enable phase-correct modulation. 0: Trailing-edge"]
10pub type PH_CORRECT_R = crate::BitReader;
11#[doc = "Field `PH_CORRECT` writer - 1: Enable phase-correct modulation. 0: Trailing-edge"]
12pub type PH_CORRECT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `A_INV` reader - Invert output A"]
14pub type A_INV_R = crate::BitReader;
15#[doc = "Field `A_INV` writer - Invert output A"]
16pub type A_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `B_INV` reader - Invert output B"]
18pub type B_INV_R = crate::BitReader;
19#[doc = "Field `B_INV` writer - Invert output B"]
20pub type B_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DIVMODE` reader - "]
22pub type DIVMODE_R = crate::FieldReader<DIVMODE_A>;
23#[doc = "  
24
25Value on reset: 0"]
26#[derive(Clone, Copy, Debug, PartialEq, Eq)]
27#[repr(u8)]
28pub enum DIVMODE_A {
29    #[doc = "0: Free-running counting at rate dictated by fractional divider"]
30    DIV = 0,
31    #[doc = "1: Fractional divider operation is gated by the PWM B pin."]
32    LEVEL = 1,
33    #[doc = "2: Counter advances with each rising edge of the PWM B pin."]
34    RISE = 2,
35    #[doc = "3: Counter advances with each falling edge of the PWM B pin."]
36    FALL = 3,
37}
38impl From<DIVMODE_A> for u8 {
39    #[inline(always)]
40    fn from(variant: DIVMODE_A) -> Self {
41        variant as _
42    }
43}
44impl crate::FieldSpec for DIVMODE_A {
45    type Ux = u8;
46}
47impl DIVMODE_R {
48    #[doc = "Get enumerated values variant"]
49    #[inline(always)]
50    pub const fn variant(&self) -> DIVMODE_A {
51        match self.bits {
52            0 => DIVMODE_A::DIV,
53            1 => DIVMODE_A::LEVEL,
54            2 => DIVMODE_A::RISE,
55            3 => DIVMODE_A::FALL,
56            _ => unreachable!(),
57        }
58    }
59    #[doc = "Free-running counting at rate dictated by fractional divider"]
60    #[inline(always)]
61    pub fn is_div(&self) -> bool {
62        *self == DIVMODE_A::DIV
63    }
64    #[doc = "Fractional divider operation is gated by the PWM B pin."]
65    #[inline(always)]
66    pub fn is_level(&self) -> bool {
67        *self == DIVMODE_A::LEVEL
68    }
69    #[doc = "Counter advances with each rising edge of the PWM B pin."]
70    #[inline(always)]
71    pub fn is_rise(&self) -> bool {
72        *self == DIVMODE_A::RISE
73    }
74    #[doc = "Counter advances with each falling edge of the PWM B pin."]
75    #[inline(always)]
76    pub fn is_fall(&self) -> bool {
77        *self == DIVMODE_A::FALL
78    }
79}
80#[doc = "Field `DIVMODE` writer - "]
81pub type DIVMODE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DIVMODE_A>;
82impl<'a, REG> DIVMODE_W<'a, REG>
83where
84    REG: crate::Writable + crate::RegisterSpec,
85    REG::Ux: From<u8>,
86{
87    #[doc = "Free-running counting at rate dictated by fractional divider"]
88    #[inline(always)]
89    pub fn div(self) -> &'a mut crate::W<REG> {
90        self.variant(DIVMODE_A::DIV)
91    }
92    #[doc = "Fractional divider operation is gated by the PWM B pin."]
93    #[inline(always)]
94    pub fn level(self) -> &'a mut crate::W<REG> {
95        self.variant(DIVMODE_A::LEVEL)
96    }
97    #[doc = "Counter advances with each rising edge of the PWM B pin."]
98    #[inline(always)]
99    pub fn rise(self) -> &'a mut crate::W<REG> {
100        self.variant(DIVMODE_A::RISE)
101    }
102    #[doc = "Counter advances with each falling edge of the PWM B pin."]
103    #[inline(always)]
104    pub fn fall(self) -> &'a mut crate::W<REG> {
105        self.variant(DIVMODE_A::FALL)
106    }
107}
108#[doc = "Field `PH_RET` reader - Retard the phase of the counter by 1 count, while it is running.  
109 Self-clearing. Write a 1, and poll until low. Counter must be running."]
110pub type PH_RET_R = crate::BitReader;
111#[doc = "Field `PH_RET` writer - Retard the phase of the counter by 1 count, while it is running.  
112 Self-clearing. Write a 1, and poll until low. Counter must be running."]
113pub type PH_RET_W<'a, REG> = crate::BitWriter<'a, REG>;
114#[doc = "Field `PH_ADV` reader - Advance the phase of the counter by 1 count, while it is running.  
115 Self-clearing. Write a 1, and poll until low. Counter must be running  
116 at less than full speed (div_int + div_frac / 16 > 1)"]
117pub type PH_ADV_R = crate::BitReader;
118#[doc = "Field `PH_ADV` writer - Advance the phase of the counter by 1 count, while it is running.  
119 Self-clearing. Write a 1, and poll until low. Counter must be running  
120 at less than full speed (div_int + div_frac / 16 > 1)"]
121pub type PH_ADV_W<'a, REG> = crate::BitWriter<'a, REG>;
122impl R {
123    #[doc = "Bit 0 - Enable the PWM channel."]
124    #[inline(always)]
125    pub fn en(&self) -> EN_R {
126        EN_R::new((self.bits & 1) != 0)
127    }
128    #[doc = "Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge"]
129    #[inline(always)]
130    pub fn ph_correct(&self) -> PH_CORRECT_R {
131        PH_CORRECT_R::new(((self.bits >> 1) & 1) != 0)
132    }
133    #[doc = "Bit 2 - Invert output A"]
134    #[inline(always)]
135    pub fn a_inv(&self) -> A_INV_R {
136        A_INV_R::new(((self.bits >> 2) & 1) != 0)
137    }
138    #[doc = "Bit 3 - Invert output B"]
139    #[inline(always)]
140    pub fn b_inv(&self) -> B_INV_R {
141        B_INV_R::new(((self.bits >> 3) & 1) != 0)
142    }
143    #[doc = "Bits 4:5"]
144    #[inline(always)]
145    pub fn divmode(&self) -> DIVMODE_R {
146        DIVMODE_R::new(((self.bits >> 4) & 3) as u8)
147    }
148    #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running.  
149 Self-clearing. Write a 1, and poll until low. Counter must be running."]
150    #[inline(always)]
151    pub fn ph_ret(&self) -> PH_RET_R {
152        PH_RET_R::new(((self.bits >> 6) & 1) != 0)
153    }
154    #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running.  
155 Self-clearing. Write a 1, and poll until low. Counter must be running  
156 at less than full speed (div_int + div_frac / 16 > 1)"]
157    #[inline(always)]
158    pub fn ph_adv(&self) -> PH_ADV_R {
159        PH_ADV_R::new(((self.bits >> 7) & 1) != 0)
160    }
161}
162impl W {
163    #[doc = "Bit 0 - Enable the PWM channel."]
164    #[inline(always)]
165    #[must_use]
166    pub fn en(&mut self) -> EN_W<CSR_SPEC> {
167        EN_W::new(self, 0)
168    }
169    #[doc = "Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge"]
170    #[inline(always)]
171    #[must_use]
172    pub fn ph_correct(&mut self) -> PH_CORRECT_W<CSR_SPEC> {
173        PH_CORRECT_W::new(self, 1)
174    }
175    #[doc = "Bit 2 - Invert output A"]
176    #[inline(always)]
177    #[must_use]
178    pub fn a_inv(&mut self) -> A_INV_W<CSR_SPEC> {
179        A_INV_W::new(self, 2)
180    }
181    #[doc = "Bit 3 - Invert output B"]
182    #[inline(always)]
183    #[must_use]
184    pub fn b_inv(&mut self) -> B_INV_W<CSR_SPEC> {
185        B_INV_W::new(self, 3)
186    }
187    #[doc = "Bits 4:5"]
188    #[inline(always)]
189    #[must_use]
190    pub fn divmode(&mut self) -> DIVMODE_W<CSR_SPEC> {
191        DIVMODE_W::new(self, 4)
192    }
193    #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running.  
194 Self-clearing. Write a 1, and poll until low. Counter must be running."]
195    #[inline(always)]
196    #[must_use]
197    pub fn ph_ret(&mut self) -> PH_RET_W<CSR_SPEC> {
198        PH_RET_W::new(self, 6)
199    }
200    #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running.  
201 Self-clearing. Write a 1, and poll until low. Counter must be running  
202 at less than full speed (div_int + div_frac / 16 > 1)"]
203    #[inline(always)]
204    #[must_use]
205    pub fn ph_adv(&mut self) -> PH_ADV_W<CSR_SPEC> {
206        PH_ADV_W::new(self, 7)
207    }
208    #[doc = r" Writes raw bits to the register."]
209    #[doc = r""]
210    #[doc = r" # Safety"]
211    #[doc = r""]
212    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
213    #[inline(always)]
214    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
215        self.bits = bits;
216        self
217    }
218}
219#[doc = "Control and status register  
220
221You can [`read`](crate::generic::Reg::read) this register and get [`csr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
222pub struct CSR_SPEC;
223impl crate::RegisterSpec for CSR_SPEC {
224    type Ux = u32;
225}
226#[doc = "`read()` method returns [`csr::R`](R) reader structure"]
227impl crate::Readable for CSR_SPEC {}
228#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"]
229impl crate::Writable for CSR_SPEC {
230    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
231    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
232}
233#[doc = "`reset()` method sets CSR to value 0"]
234impl crate::Resettable for CSR_SPEC {
235    const RESET_VALUE: u32 = 0;
236}
rp2040_pac/pwm/ch/csr.rs

rp2040_pac/pwm/ch/
csr.rs
