rp2040_pac/i2c0/
ic_tar.rs

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1#[doc = "Register `IC_TAR` reader"]
2pub type R = crate::R<IC_TAR_SPEC>;
3#[doc = "Register `IC_TAR` writer"]
4pub type W = crate::W<IC_TAR_SPEC>;
5#[doc = "Field `IC_TAR` reader - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.  
6
7 If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."]
8pub type IC_TAR_R = crate::FieldReader<u16>;
9#[doc = "Field `IC_TAR` writer - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.  
10
11 If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."]
12pub type IC_TAR_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
13#[doc = "Field `GC_OR_START` reader - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"]
14pub type GC_OR_START_R = crate::BitReader<GC_OR_START_A>;
15#[doc = "If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0  
16
17Value on reset: 0"]
18#[derive(Clone, Copy, Debug, PartialEq, Eq)]
19pub enum GC_OR_START_A {
20    #[doc = "0: GENERAL_CALL byte transmission"]
21    GENERAL_CALL = 0,
22    #[doc = "1: START byte transmission"]
23    START_BYTE = 1,
24}
25impl From<GC_OR_START_A> for bool {
26    #[inline(always)]
27    fn from(variant: GC_OR_START_A) -> Self {
28        variant as u8 != 0
29    }
30}
31impl GC_OR_START_R {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> GC_OR_START_A {
35        match self.bits {
36            false => GC_OR_START_A::GENERAL_CALL,
37            true => GC_OR_START_A::START_BYTE,
38        }
39    }
40    #[doc = "GENERAL_CALL byte transmission"]
41    #[inline(always)]
42    pub fn is_general_call(&self) -> bool {
43        *self == GC_OR_START_A::GENERAL_CALL
44    }
45    #[doc = "START byte transmission"]
46    #[inline(always)]
47    pub fn is_start_byte(&self) -> bool {
48        *self == GC_OR_START_A::START_BYTE
49    }
50}
51#[doc = "Field `GC_OR_START` writer - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"]
52pub type GC_OR_START_W<'a, REG> = crate::BitWriter<'a, REG, GC_OR_START_A>;
53impl<'a, REG> GC_OR_START_W<'a, REG>
54where
55    REG: crate::Writable + crate::RegisterSpec,
56{
57    #[doc = "GENERAL_CALL byte transmission"]
58    #[inline(always)]
59    pub fn general_call(self) -> &'a mut crate::W<REG> {
60        self.variant(GC_OR_START_A::GENERAL_CALL)
61    }
62    #[doc = "START byte transmission"]
63    #[inline(always)]
64    pub fn start_byte(self) -> &'a mut crate::W<REG> {
65        self.variant(GC_OR_START_A::START_BYTE)
66    }
67}
68#[doc = "Field `SPECIAL` reader - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"]
69pub type SPECIAL_R = crate::BitReader<SPECIAL_A>;
70#[doc = "This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0  
71
72Value on reset: 0"]
73#[derive(Clone, Copy, Debug, PartialEq, Eq)]
74pub enum SPECIAL_A {
75    #[doc = "0: Disables programming of GENERAL_CALL or START_BYTE transmission"]
76    DISABLED = 0,
77    #[doc = "1: Enables programming of GENERAL_CALL or START_BYTE transmission"]
78    ENABLED = 1,
79}
80impl From<SPECIAL_A> for bool {
81    #[inline(always)]
82    fn from(variant: SPECIAL_A) -> Self {
83        variant as u8 != 0
84    }
85}
86impl SPECIAL_R {
87    #[doc = "Get enumerated values variant"]
88    #[inline(always)]
89    pub const fn variant(&self) -> SPECIAL_A {
90        match self.bits {
91            false => SPECIAL_A::DISABLED,
92            true => SPECIAL_A::ENABLED,
93        }
94    }
95    #[doc = "Disables programming of GENERAL_CALL or START_BYTE transmission"]
96    #[inline(always)]
97    pub fn is_disabled(&self) -> bool {
98        *self == SPECIAL_A::DISABLED
99    }
100    #[doc = "Enables programming of GENERAL_CALL or START_BYTE transmission"]
101    #[inline(always)]
102    pub fn is_enabled(&self) -> bool {
103        *self == SPECIAL_A::ENABLED
104    }
105}
106#[doc = "Field `SPECIAL` writer - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"]
107pub type SPECIAL_W<'a, REG> = crate::BitWriter<'a, REG, SPECIAL_A>;
108impl<'a, REG> SPECIAL_W<'a, REG>
109where
110    REG: crate::Writable + crate::RegisterSpec,
111{
112    #[doc = "Disables programming of GENERAL_CALL or START_BYTE transmission"]
113    #[inline(always)]
114    pub fn disabled(self) -> &'a mut crate::W<REG> {
115        self.variant(SPECIAL_A::DISABLED)
116    }
117    #[doc = "Enables programming of GENERAL_CALL or START_BYTE transmission"]
118    #[inline(always)]
119    pub fn enabled(self) -> &'a mut crate::W<REG> {
120        self.variant(SPECIAL_A::ENABLED)
121    }
122}
123impl R {
124    #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.  
125
126 If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."]
127    #[inline(always)]
128    pub fn ic_tar(&self) -> IC_TAR_R {
129        IC_TAR_R::new((self.bits & 0x03ff) as u16)
130    }
131    #[doc = "Bit 10 - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"]
132    #[inline(always)]
133    pub fn gc_or_start(&self) -> GC_OR_START_R {
134        GC_OR_START_R::new(((self.bits >> 10) & 1) != 0)
135    }
136    #[doc = "Bit 11 - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"]
137    #[inline(always)]
138    pub fn special(&self) -> SPECIAL_R {
139        SPECIAL_R::new(((self.bits >> 11) & 1) != 0)
140    }
141}
142impl W {
143    #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.  
144
145 If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."]
146    #[inline(always)]
147    #[must_use]
148    pub fn ic_tar(&mut self) -> IC_TAR_W<IC_TAR_SPEC> {
149        IC_TAR_W::new(self, 0)
150    }
151    #[doc = "Bit 10 - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"]
152    #[inline(always)]
153    #[must_use]
154    pub fn gc_or_start(&mut self) -> GC_OR_START_W<IC_TAR_SPEC> {
155        GC_OR_START_W::new(self, 10)
156    }
157    #[doc = "Bit 11 - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"]
158    #[inline(always)]
159    #[must_use]
160    pub fn special(&mut self) -> SPECIAL_W<IC_TAR_SPEC> {
161        SPECIAL_W::new(self, 11)
162    }
163    #[doc = r" Writes raw bits to the register."]
164    #[doc = r""]
165    #[doc = r" # Safety"]
166    #[doc = r""]
167    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
168    #[inline(always)]
169    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
170        self.bits = bits;
171        self
172    }
173}
174#[doc = "I2C Target Address Register  
175
176 This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\]
177is set to 0.  
178
179 Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.  
180
181You can [`read`](crate::generic::Reg::read) this register and get [`ic_tar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct IC_TAR_SPEC;
183impl crate::RegisterSpec for IC_TAR_SPEC {
184    type Ux = u32;
185}
186#[doc = "`read()` method returns [`ic_tar::R`](R) reader structure"]
187impl crate::Readable for IC_TAR_SPEC {}
188#[doc = "`write(|w| ..)` method takes [`ic_tar::W`](W) writer structure"]
189impl crate::Writable for IC_TAR_SPEC {
190    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
191    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
192}
193#[doc = "`reset()` method sets IC_TAR to value 0x55"]
194impl crate::Resettable for IC_TAR_SPEC {
195    const RESET_VALUE: u32 = 0x55;
196}
rp2040_pac/i2c0/ic_tar.rs

rp2040_pac/i2c0/
ic_tar.rs
