rp2040_pac/uart0/
uartimsc.rs

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1#[doc = "Register `UARTIMSC` reader"]
2pub type R = crate::R<UARTIMSC_SPEC>;
3#[doc = "Register `UARTIMSC` writer"]
4pub type W = crate::W<UARTIMSC_SPEC>;
5#[doc = "Field `RIMIM` reader - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."]
6pub type RIMIM_R = crate::BitReader;
7#[doc = "Field `RIMIM` writer - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."]
8pub type RIMIM_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CTSMIM` reader - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."]
10pub type CTSMIM_R = crate::BitReader;
11#[doc = "Field `CTSMIM` writer - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."]
12pub type CTSMIM_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DCDMIM` reader - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."]
14pub type DCDMIM_R = crate::BitReader;
15#[doc = "Field `DCDMIM` writer - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."]
16pub type DCDMIM_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DSRMIM` reader - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."]
18pub type DSRMIM_R = crate::BitReader;
19#[doc = "Field `DSRMIM` writer - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."]
20pub type DSRMIM_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RXIM` reader - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."]
22pub type RXIM_R = crate::BitReader;
23#[doc = "Field `RXIM` writer - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."]
24pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TXIM` reader - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."]
26pub type TXIM_R = crate::BitReader;
27#[doc = "Field `TXIM` writer - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."]
28pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RTIM` reader - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."]
30pub type RTIM_R = crate::BitReader;
31#[doc = "Field `RTIM` writer - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."]
32pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FEIM` reader - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."]
34pub type FEIM_R = crate::BitReader;
35#[doc = "Field `FEIM` writer - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."]
36pub type FEIM_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `PEIM` reader - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."]
38pub type PEIM_R = crate::BitReader;
39#[doc = "Field `PEIM` writer - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."]
40pub type PEIM_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `BEIM` reader - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."]
42pub type BEIM_R = crate::BitReader;
43#[doc = "Field `BEIM` writer - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."]
44pub type BEIM_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `OEIM` reader - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."]
46pub type OEIM_R = crate::BitReader;
47#[doc = "Field `OEIM` writer - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."]
48pub type OEIM_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50    #[doc = "Bit 0 - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."]
51    #[inline(always)]
52    pub fn rimim(&self) -> RIMIM_R {
53        RIMIM_R::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bit 1 - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."]
56    #[inline(always)]
57    pub fn ctsmim(&self) -> CTSMIM_R {
58        CTSMIM_R::new(((self.bits >> 1) & 1) != 0)
59    }
60    #[doc = "Bit 2 - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."]
61    #[inline(always)]
62    pub fn dcdmim(&self) -> DCDMIM_R {
63        DCDMIM_R::new(((self.bits >> 2) & 1) != 0)
64    }
65    #[doc = "Bit 3 - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."]
66    #[inline(always)]
67    pub fn dsrmim(&self) -> DSRMIM_R {
68        DSRMIM_R::new(((self.bits >> 3) & 1) != 0)
69    }
70    #[doc = "Bit 4 - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."]
71    #[inline(always)]
72    pub fn rxim(&self) -> RXIM_R {
73        RXIM_R::new(((self.bits >> 4) & 1) != 0)
74    }
75    #[doc = "Bit 5 - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."]
76    #[inline(always)]
77    pub fn txim(&self) -> TXIM_R {
78        TXIM_R::new(((self.bits >> 5) & 1) != 0)
79    }
80    #[doc = "Bit 6 - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."]
81    #[inline(always)]
82    pub fn rtim(&self) -> RTIM_R {
83        RTIM_R::new(((self.bits >> 6) & 1) != 0)
84    }
85    #[doc = "Bit 7 - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."]
86    #[inline(always)]
87    pub fn feim(&self) -> FEIM_R {
88        FEIM_R::new(((self.bits >> 7) & 1) != 0)
89    }
90    #[doc = "Bit 8 - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."]
91    #[inline(always)]
92    pub fn peim(&self) -> PEIM_R {
93        PEIM_R::new(((self.bits >> 8) & 1) != 0)
94    }
95    #[doc = "Bit 9 - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."]
96    #[inline(always)]
97    pub fn beim(&self) -> BEIM_R {
98        BEIM_R::new(((self.bits >> 9) & 1) != 0)
99    }
100    #[doc = "Bit 10 - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."]
101    #[inline(always)]
102    pub fn oeim(&self) -> OEIM_R {
103        OEIM_R::new(((self.bits >> 10) & 1) != 0)
104    }
105}
106impl W {
107    #[doc = "Bit 0 - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."]
108    #[inline(always)]
109    #[must_use]
110    pub fn rimim(&mut self) -> RIMIM_W<UARTIMSC_SPEC> {
111        RIMIM_W::new(self, 0)
112    }
113    #[doc = "Bit 1 - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."]
114    #[inline(always)]
115    #[must_use]
116    pub fn ctsmim(&mut self) -> CTSMIM_W<UARTIMSC_SPEC> {
117        CTSMIM_W::new(self, 1)
118    }
119    #[doc = "Bit 2 - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."]
120    #[inline(always)]
121    #[must_use]
122    pub fn dcdmim(&mut self) -> DCDMIM_W<UARTIMSC_SPEC> {
123        DCDMIM_W::new(self, 2)
124    }
125    #[doc = "Bit 3 - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."]
126    #[inline(always)]
127    #[must_use]
128    pub fn dsrmim(&mut self) -> DSRMIM_W<UARTIMSC_SPEC> {
129        DSRMIM_W::new(self, 3)
130    }
131    #[doc = "Bit 4 - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."]
132    #[inline(always)]
133    #[must_use]
134    pub fn rxim(&mut self) -> RXIM_W<UARTIMSC_SPEC> {
135        RXIM_W::new(self, 4)
136    }
137    #[doc = "Bit 5 - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."]
138    #[inline(always)]
139    #[must_use]
140    pub fn txim(&mut self) -> TXIM_W<UARTIMSC_SPEC> {
141        TXIM_W::new(self, 5)
142    }
143    #[doc = "Bit 6 - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."]
144    #[inline(always)]
145    #[must_use]
146    pub fn rtim(&mut self) -> RTIM_W<UARTIMSC_SPEC> {
147        RTIM_W::new(self, 6)
148    }
149    #[doc = "Bit 7 - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."]
150    #[inline(always)]
151    #[must_use]
152    pub fn feim(&mut self) -> FEIM_W<UARTIMSC_SPEC> {
153        FEIM_W::new(self, 7)
154    }
155    #[doc = "Bit 8 - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."]
156    #[inline(always)]
157    #[must_use]
158    pub fn peim(&mut self) -> PEIM_W<UARTIMSC_SPEC> {
159        PEIM_W::new(self, 8)
160    }
161    #[doc = "Bit 9 - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."]
162    #[inline(always)]
163    #[must_use]
164    pub fn beim(&mut self) -> BEIM_W<UARTIMSC_SPEC> {
165        BEIM_W::new(self, 9)
166    }
167    #[doc = "Bit 10 - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."]
168    #[inline(always)]
169    #[must_use]
170    pub fn oeim(&mut self) -> OEIM_W<UARTIMSC_SPEC> {
171        OEIM_W::new(self, 10)
172    }
173    #[doc = r" Writes raw bits to the register."]
174    #[doc = r""]
175    #[doc = r" # Safety"]
176    #[doc = r""]
177    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
178    #[inline(always)]
179    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
180        self.bits = bits;
181        self
182    }
183}
184#[doc = "Interrupt Mask Set/Clear Register, UARTIMSC  
185
186You can [`read`](crate::generic::Reg::read) this register and get [`uartimsc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartimsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
187pub struct UARTIMSC_SPEC;
188impl crate::RegisterSpec for UARTIMSC_SPEC {
189    type Ux = u32;
190}
191#[doc = "`read()` method returns [`uartimsc::R`](R) reader structure"]
192impl crate::Readable for UARTIMSC_SPEC {}
193#[doc = "`write(|w| ..)` method takes [`uartimsc::W`](W) writer structure"]
194impl crate::Writable for UARTIMSC_SPEC {
195    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
196    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
197}
198#[doc = "`reset()` method sets UARTIMSC to value 0"]
199impl crate::Resettable for UARTIMSC_SPEC {
200    const RESET_VALUE: u32 = 0;
201}
rp2040_pac/uart0/uartimsc.rs

rp2040_pac/uart0/
uartimsc.rs
