rp2040_pac/
xip_ssi.rs

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1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    ctrlr0: CTRLR0,
5    ctrlr1: CTRLR1,
6    ssienr: SSIENR,
7    mwcr: MWCR,
8    ser: SER,
9    baudr: BAUDR,
10    txftlr: TXFTLR,
11    rxftlr: RXFTLR,
12    txflr: TXFLR,
13    rxflr: RXFLR,
14    sr: SR,
15    imr: IMR,
16    isr: ISR,
17    risr: RISR,
18    txoicr: TXOICR,
19    rxoicr: RXOICR,
20    rxuicr: RXUICR,
21    msticr: MSTICR,
22    icr: ICR,
23    dmacr: DMACR,
24    dmatdlr: DMATDLR,
25    dmardlr: DMARDLR,
26    idr: IDR,
27    ssi_version_id: SSI_VERSION_ID,
28    dr0: DR0,
29    _reserved25: [u8; 0x8c],
30    rx_sample_dly: RX_SAMPLE_DLY,
31    spi_ctrlr0: SPI_CTRLR0,
32    txd_drive_edge: TXD_DRIVE_EDGE,
33}
34impl RegisterBlock {
35    #[doc = "0x00 - Control register 0"]
36    #[inline(always)]
37    pub const fn ctrlr0(&self) -> &CTRLR0 {
38        &self.ctrlr0
39    }
40    #[doc = "0x04 - Master Control register 1"]
41    #[inline(always)]
42    pub const fn ctrlr1(&self) -> &CTRLR1 {
43        &self.ctrlr1
44    }
45    #[doc = "0x08 - SSI Enable"]
46    #[inline(always)]
47    pub const fn ssienr(&self) -> &SSIENR {
48        &self.ssienr
49    }
50    #[doc = "0x0c - Microwire Control"]
51    #[inline(always)]
52    pub const fn mwcr(&self) -> &MWCR {
53        &self.mwcr
54    }
55    #[doc = "0x10 - Slave enable"]
56    #[inline(always)]
57    pub const fn ser(&self) -> &SER {
58        &self.ser
59    }
60    #[doc = "0x14 - Baud rate"]
61    #[inline(always)]
62    pub const fn baudr(&self) -> &BAUDR {
63        &self.baudr
64    }
65    #[doc = "0x18 - TX FIFO threshold level"]
66    #[inline(always)]
67    pub const fn txftlr(&self) -> &TXFTLR {
68        &self.txftlr
69    }
70    #[doc = "0x1c - RX FIFO threshold level"]
71    #[inline(always)]
72    pub const fn rxftlr(&self) -> &RXFTLR {
73        &self.rxftlr
74    }
75    #[doc = "0x20 - TX FIFO level"]
76    #[inline(always)]
77    pub const fn txflr(&self) -> &TXFLR {
78        &self.txflr
79    }
80    #[doc = "0x24 - RX FIFO level"]
81    #[inline(always)]
82    pub const fn rxflr(&self) -> &RXFLR {
83        &self.rxflr
84    }
85    #[doc = "0x28 - Status register"]
86    #[inline(always)]
87    pub const fn sr(&self) -> &SR {
88        &self.sr
89    }
90    #[doc = "0x2c - Interrupt mask"]
91    #[inline(always)]
92    pub const fn imr(&self) -> &IMR {
93        &self.imr
94    }
95    #[doc = "0x30 - Interrupt status"]
96    #[inline(always)]
97    pub const fn isr(&self) -> &ISR {
98        &self.isr
99    }
100    #[doc = "0x34 - Raw interrupt status"]
101    #[inline(always)]
102    pub const fn risr(&self) -> &RISR {
103        &self.risr
104    }
105    #[doc = "0x38 - TX FIFO overflow interrupt clear"]
106    #[inline(always)]
107    pub const fn txoicr(&self) -> &TXOICR {
108        &self.txoicr
109    }
110    #[doc = "0x3c - RX FIFO overflow interrupt clear"]
111    #[inline(always)]
112    pub const fn rxoicr(&self) -> &RXOICR {
113        &self.rxoicr
114    }
115    #[doc = "0x40 - RX FIFO underflow interrupt clear"]
116    #[inline(always)]
117    pub const fn rxuicr(&self) -> &RXUICR {
118        &self.rxuicr
119    }
120    #[doc = "0x44 - Multi-master interrupt clear"]
121    #[inline(always)]
122    pub const fn msticr(&self) -> &MSTICR {
123        &self.msticr
124    }
125    #[doc = "0x48 - Interrupt clear"]
126    #[inline(always)]
127    pub const fn icr(&self) -> &ICR {
128        &self.icr
129    }
130    #[doc = "0x4c - DMA control"]
131    #[inline(always)]
132    pub const fn dmacr(&self) -> &DMACR {
133        &self.dmacr
134    }
135    #[doc = "0x50 - DMA TX data level"]
136    #[inline(always)]
137    pub const fn dmatdlr(&self) -> &DMATDLR {
138        &self.dmatdlr
139    }
140    #[doc = "0x54 - DMA RX data level"]
141    #[inline(always)]
142    pub const fn dmardlr(&self) -> &DMARDLR {
143        &self.dmardlr
144    }
145    #[doc = "0x58 - Identification register"]
146    #[inline(always)]
147    pub const fn idr(&self) -> &IDR {
148        &self.idr
149    }
150    #[doc = "0x5c - Version ID"]
151    #[inline(always)]
152    pub const fn ssi_version_id(&self) -> &SSI_VERSION_ID {
153        &self.ssi_version_id
154    }
155    #[doc = "0x60 - Data Register 0 (of 36)"]
156    #[inline(always)]
157    pub const fn dr0(&self) -> &DR0 {
158        &self.dr0
159    }
160    #[doc = "0xf0 - RX sample delay"]
161    #[inline(always)]
162    pub const fn rx_sample_dly(&self) -> &RX_SAMPLE_DLY {
163        &self.rx_sample_dly
164    }
165    #[doc = "0xf4 - SPI control"]
166    #[inline(always)]
167    pub const fn spi_ctrlr0(&self) -> &SPI_CTRLR0 {
168        &self.spi_ctrlr0
169    }
170    #[doc = "0xf8 - TX drive edge"]
171    #[inline(always)]
172    pub const fn txd_drive_edge(&self) -> &TXD_DRIVE_EDGE {
173        &self.txd_drive_edge
174    }
175}
176#[doc = "CTRLR0 (rw) register accessor: Control register 0  
177
178You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
179
180For information about available fields see [`mod@ctrlr0`]
181module"]
182pub type CTRLR0 = crate::Reg<ctrlr0::CTRLR0_SPEC>;
183#[doc = "Control register 0"]
184pub mod ctrlr0;
185#[doc = "CTRLR1 (rw) register accessor: Master Control register 1  
186
187You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
188
189For information about available fields see [`mod@ctrlr1`]
190module"]
191pub type CTRLR1 = crate::Reg<ctrlr1::CTRLR1_SPEC>;
192#[doc = "Master Control register 1"]
193pub mod ctrlr1;
194#[doc = "SSIENR (rw) register accessor: SSI Enable  
195
196You can [`read`](crate::generic::Reg::read) this register and get [`ssienr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssienr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
197
198For information about available fields see [`mod@ssienr`]
199module"]
200pub type SSIENR = crate::Reg<ssienr::SSIENR_SPEC>;
201#[doc = "SSI Enable"]
202pub mod ssienr;
203#[doc = "MWCR (rw) register accessor: Microwire Control  
204
205You can [`read`](crate::generic::Reg::read) this register and get [`mwcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mwcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
206
207For information about available fields see [`mod@mwcr`]
208module"]
209pub type MWCR = crate::Reg<mwcr::MWCR_SPEC>;
210#[doc = "Microwire Control"]
211pub mod mwcr;
212#[doc = "SER (rw) register accessor: Slave enable  
213
214You can [`read`](crate::generic::Reg::read) this register and get [`ser::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ser::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
215
216For information about available fields see [`mod@ser`]
217module"]
218pub type SER = crate::Reg<ser::SER_SPEC>;
219#[doc = "Slave enable"]
220pub mod ser;
221#[doc = "BAUDR (rw) register accessor: Baud rate  
222
223You can [`read`](crate::generic::Reg::read) this register and get [`baudr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
224
225For information about available fields see [`mod@baudr`]
226module"]
227pub type BAUDR = crate::Reg<baudr::BAUDR_SPEC>;
228#[doc = "Baud rate"]
229pub mod baudr;
230#[doc = "TXFTLR (rw) register accessor: TX FIFO threshold level  
231
232You can [`read`](crate::generic::Reg::read) this register and get [`txftlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txftlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
233
234For information about available fields see [`mod@txftlr`]
235module"]
236pub type TXFTLR = crate::Reg<txftlr::TXFTLR_SPEC>;
237#[doc = "TX FIFO threshold level"]
238pub mod txftlr;
239#[doc = "RXFTLR (rw) register accessor: RX FIFO threshold level  
240
241You can [`read`](crate::generic::Reg::read) this register and get [`rxftlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxftlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
242
243For information about available fields see [`mod@rxftlr`]
244module"]
245pub type RXFTLR = crate::Reg<rxftlr::RXFTLR_SPEC>;
246#[doc = "RX FIFO threshold level"]
247pub mod rxftlr;
248#[doc = "TXFLR (r) register accessor: TX FIFO level  
249
250You can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
251
252For information about available fields see [`mod@txflr`]
253module"]
254pub type TXFLR = crate::Reg<txflr::TXFLR_SPEC>;
255#[doc = "TX FIFO level"]
256pub mod txflr;
257#[doc = "RXFLR (r) register accessor: RX FIFO level  
258
259You can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
260
261For information about available fields see [`mod@rxflr`]
262module"]
263pub type RXFLR = crate::Reg<rxflr::RXFLR_SPEC>;
264#[doc = "RX FIFO level"]
265pub mod rxflr;
266#[doc = "SR (r) register accessor: Status register  
267
268You can [`read`](crate::generic::Reg::read) this register and get [`sr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
269
270For information about available fields see [`mod@sr`]
271module"]
272pub type SR = crate::Reg<sr::SR_SPEC>;
273#[doc = "Status register"]
274pub mod sr;
275#[doc = "IMR (rw) register accessor: Interrupt mask  
276
277You can [`read`](crate::generic::Reg::read) this register and get [`imr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
278
279For information about available fields see [`mod@imr`]
280module"]
281pub type IMR = crate::Reg<imr::IMR_SPEC>;
282#[doc = "Interrupt mask"]
283pub mod imr;
284#[doc = "ISR (r) register accessor: Interrupt status  
285
286You can [`read`](crate::generic::Reg::read) this register and get [`isr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
287
288For information about available fields see [`mod@isr`]
289module"]
290pub type ISR = crate::Reg<isr::ISR_SPEC>;
291#[doc = "Interrupt status"]
292pub mod isr;
293#[doc = "RISR (r) register accessor: Raw interrupt status  
294
295You can [`read`](crate::generic::Reg::read) this register and get [`risr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
296
297For information about available fields see [`mod@risr`]
298module"]
299pub type RISR = crate::Reg<risr::RISR_SPEC>;
300#[doc = "Raw interrupt status"]
301pub mod risr;
302#[doc = "TXOICR (r) register accessor: TX FIFO overflow interrupt clear  
303
304You can [`read`](crate::generic::Reg::read) this register and get [`txoicr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
305
306For information about available fields see [`mod@txoicr`]
307module"]
308pub type TXOICR = crate::Reg<txoicr::TXOICR_SPEC>;
309#[doc = "TX FIFO overflow interrupt clear"]
310pub mod txoicr;
311#[doc = "RXOICR (r) register accessor: RX FIFO overflow interrupt clear  
312
313You can [`read`](crate::generic::Reg::read) this register and get [`rxoicr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
314
315For information about available fields see [`mod@rxoicr`]
316module"]
317pub type RXOICR = crate::Reg<rxoicr::RXOICR_SPEC>;
318#[doc = "RX FIFO overflow interrupt clear"]
319pub mod rxoicr;
320#[doc = "RXUICR (r) register accessor: RX FIFO underflow interrupt clear  
321
322You can [`read`](crate::generic::Reg::read) this register and get [`rxuicr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
323
324For information about available fields see [`mod@rxuicr`]
325module"]
326pub type RXUICR = crate::Reg<rxuicr::RXUICR_SPEC>;
327#[doc = "RX FIFO underflow interrupt clear"]
328pub mod rxuicr;
329#[doc = "MSTICR (r) register accessor: Multi-master interrupt clear  
330
331You can [`read`](crate::generic::Reg::read) this register and get [`msticr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
332
333For information about available fields see [`mod@msticr`]
334module"]
335pub type MSTICR = crate::Reg<msticr::MSTICR_SPEC>;
336#[doc = "Multi-master interrupt clear"]
337pub mod msticr;
338#[doc = "ICR (r) register accessor: Interrupt clear  
339
340You can [`read`](crate::generic::Reg::read) this register and get [`icr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
341
342For information about available fields see [`mod@icr`]
343module"]
344pub type ICR = crate::Reg<icr::ICR_SPEC>;
345#[doc = "Interrupt clear"]
346pub mod icr;
347#[doc = "DMACR (rw) register accessor: DMA control  
348
349You can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
350
351For information about available fields see [`mod@dmacr`]
352module"]
353pub type DMACR = crate::Reg<dmacr::DMACR_SPEC>;
354#[doc = "DMA control"]
355pub mod dmacr;
356#[doc = "DMATDLR (rw) register accessor: DMA TX data level  
357
358You can [`read`](crate::generic::Reg::read) this register and get [`dmatdlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatdlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
359
360For information about available fields see [`mod@dmatdlr`]
361module"]
362pub type DMATDLR = crate::Reg<dmatdlr::DMATDLR_SPEC>;
363#[doc = "DMA TX data level"]
364pub mod dmatdlr;
365#[doc = "DMARDLR (rw) register accessor: DMA RX data level  
366
367You can [`read`](crate::generic::Reg::read) this register and get [`dmardlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmardlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
368
369For information about available fields see [`mod@dmardlr`]
370module"]
371pub type DMARDLR = crate::Reg<dmardlr::DMARDLR_SPEC>;
372#[doc = "DMA RX data level"]
373pub mod dmardlr;
374#[doc = "IDR (r) register accessor: Identification register  
375
376You can [`read`](crate::generic::Reg::read) this register and get [`idr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
377
378For information about available fields see [`mod@idr`]
379module"]
380pub type IDR = crate::Reg<idr::IDR_SPEC>;
381#[doc = "Identification register"]
382pub mod idr;
383#[doc = "SSI_VERSION_ID (r) register accessor: Version ID  
384
385You can [`read`](crate::generic::Reg::read) this register and get [`ssi_version_id::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
386
387For information about available fields see [`mod@ssi_version_id`]
388module"]
389pub type SSI_VERSION_ID = crate::Reg<ssi_version_id::SSI_VERSION_ID_SPEC>;
390#[doc = "Version ID"]
391pub mod ssi_version_id;
392#[doc = "DR0 (rw) register accessor: Data Register 0 (of 36)  
393
394You can [`read`](crate::generic::Reg::read) this register and get [`dr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
395
396For information about available fields see [`mod@dr0`]
397module"]
398pub type DR0 = crate::Reg<dr0::DR0_SPEC>;
399#[doc = "Data Register 0 (of 36)"]
400pub mod dr0;
401#[doc = "RX_SAMPLE_DLY (rw) register accessor: RX sample delay  
402
403You can [`read`](crate::generic::Reg::read) this register and get [`rx_sample_dly::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_sample_dly::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
404
405For information about available fields see [`mod@rx_sample_dly`]
406module"]
407pub type RX_SAMPLE_DLY = crate::Reg<rx_sample_dly::RX_SAMPLE_DLY_SPEC>;
408#[doc = "RX sample delay"]
409pub mod rx_sample_dly;
410#[doc = "SPI_CTRLR0 (rw) register accessor: SPI control  
411
412You can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrlr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrlr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
413
414For information about available fields see [`mod@spi_ctrlr0`]
415module"]
416pub type SPI_CTRLR0 = crate::Reg<spi_ctrlr0::SPI_CTRLR0_SPEC>;
417#[doc = "SPI control"]
418pub mod spi_ctrlr0;
419#[doc = "TXD_DRIVE_EDGE (rw) register accessor: TX drive edge  
420
421You can [`read`](crate::generic::Reg::read) this register and get [`txd_drive_edge::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txd_drive_edge::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
422
423For information about available fields see [`mod@txd_drive_edge`]
424module"]
425pub type TXD_DRIVE_EDGE = crate::Reg<txd_drive_edge::TXD_DRIVE_EDGE_SPEC>;
426#[doc = "TX drive edge"]
427pub mod txd_drive_edge;
rp2040_pac/xip_ssi.rs

rp2040_pac/
xip_ssi.rs
