rp2040_pac/ppb/
ccr.rs

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1#[doc = "Register `CCR` reader"]
2pub type R = crate::R<CCR_SPEC>;
3#[doc = "Field `UNALIGN_TRP` reader - Always reads as one, indicates that all unaligned accesses generate a HardFault."]
4pub type UNALIGN_TRP_R = crate::BitReader;
5#[doc = "Field `STKALIGN` reader - Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit\\[9\\]
6of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment."]
7pub type STKALIGN_R = crate::BitReader;
8impl R {
9    #[doc = "Bit 3 - Always reads as one, indicates that all unaligned accesses generate a HardFault."]
10    #[inline(always)]
11    pub fn unalign_trp(&self) -> UNALIGN_TRP_R {
12        UNALIGN_TRP_R::new(((self.bits >> 3) & 1) != 0)
13    }
14    #[doc = "Bit 9 - Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit\\[9\\]
15of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment."]
16    #[inline(always)]
17    pub fn stkalign(&self) -> STKALIGN_R {
18        STKALIGN_R::new(((self.bits >> 9) & 1) != 0)
19    }
20}
21#[doc = "The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.  
22
23You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24pub struct CCR_SPEC;
25impl crate::RegisterSpec for CCR_SPEC {
26    type Ux = u32;
27}
28#[doc = "`read()` method returns [`ccr::R`](R) reader structure"]
29impl crate::Readable for CCR_SPEC {}
30#[doc = "`reset()` method sets CCR to value 0"]
31impl crate::Resettable for CCR_SPEC {
32    const RESET_VALUE: u32 = 0;
33}
rp2040_pac/ppb/ccr.rs

rp2040_pac/ppb/
ccr.rs
