rp2040_pac/i2c0/
ic_con.rs

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1#[doc = "Register `IC_CON` reader"]
2pub type R = crate::R<IC_CON_SPEC>;
3#[doc = "Register `IC_CON` writer"]
4pub type W = crate::W<IC_CON_SPEC>;
5#[doc = "Field `MASTER_MODE` reader - This bit controls whether the DW_apb_i2c master is enabled.  
6
7 NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."]
8pub type MASTER_MODE_R = crate::BitReader<MASTER_MODE_A>;
9#[doc = "This bit controls whether the DW_apb_i2c master is enabled.  
10
11 NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.  
12
13Value on reset: 1"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15pub enum MASTER_MODE_A {
16    #[doc = "0: Master mode is disabled"]
17    DISABLED = 0,
18    #[doc = "1: Master mode is enabled"]
19    ENABLED = 1,
20}
21impl From<MASTER_MODE_A> for bool {
22    #[inline(always)]
23    fn from(variant: MASTER_MODE_A) -> Self {
24        variant as u8 != 0
25    }
26}
27impl MASTER_MODE_R {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> MASTER_MODE_A {
31        match self.bits {
32            false => MASTER_MODE_A::DISABLED,
33            true => MASTER_MODE_A::ENABLED,
34        }
35    }
36    #[doc = "Master mode is disabled"]
37    #[inline(always)]
38    pub fn is_disabled(&self) -> bool {
39        *self == MASTER_MODE_A::DISABLED
40    }
41    #[doc = "Master mode is enabled"]
42    #[inline(always)]
43    pub fn is_enabled(&self) -> bool {
44        *self == MASTER_MODE_A::ENABLED
45    }
46}
47#[doc = "Field `MASTER_MODE` writer - This bit controls whether the DW_apb_i2c master is enabled.  
48
49 NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."]
50pub type MASTER_MODE_W<'a, REG> = crate::BitWriter<'a, REG, MASTER_MODE_A>;
51impl<'a, REG> MASTER_MODE_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "Master mode is disabled"]
56    #[inline(always)]
57    pub fn disabled(self) -> &'a mut crate::W<REG> {
58        self.variant(MASTER_MODE_A::DISABLED)
59    }
60    #[doc = "Master mode is enabled"]
61    #[inline(always)]
62    pub fn enabled(self) -> &'a mut crate::W<REG> {
63        self.variant(MASTER_MODE_A::ENABLED)
64    }
65}
66#[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.  
67
68 This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.  
69
70 1: standard mode (100 kbit/s)  
71
72 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)  
73
74 3: high speed mode (3.4 Mbit/s)  
75
76 Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
77pub type SPEED_R = crate::FieldReader<SPEED_A>;
78#[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.  
79
80 This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.  
81
82 1: standard mode (100 kbit/s)  
83
84 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)  
85
86 3: high speed mode (3.4 Mbit/s)  
87
88 Note: This field is not applicable when IC_ULTRA_FAST_MODE=1  
89
90Value on reset: 2"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92#[repr(u8)]
93pub enum SPEED_A {
94    #[doc = "1: Standard Speed mode of operation"]
95    STANDARD = 1,
96    #[doc = "2: Fast or Fast Plus mode of operation"]
97    FAST = 2,
98    #[doc = "3: High Speed mode of operation"]
99    HIGH = 3,
100}
101impl From<SPEED_A> for u8 {
102    #[inline(always)]
103    fn from(variant: SPEED_A) -> Self {
104        variant as _
105    }
106}
107impl crate::FieldSpec for SPEED_A {
108    type Ux = u8;
109}
110impl SPEED_R {
111    #[doc = "Get enumerated values variant"]
112    #[inline(always)]
113    pub const fn variant(&self) -> Option<SPEED_A> {
114        match self.bits {
115            1 => Some(SPEED_A::STANDARD),
116            2 => Some(SPEED_A::FAST),
117            3 => Some(SPEED_A::HIGH),
118            _ => None,
119        }
120    }
121    #[doc = "Standard Speed mode of operation"]
122    #[inline(always)]
123    pub fn is_standard(&self) -> bool {
124        *self == SPEED_A::STANDARD
125    }
126    #[doc = "Fast or Fast Plus mode of operation"]
127    #[inline(always)]
128    pub fn is_fast(&self) -> bool {
129        *self == SPEED_A::FAST
130    }
131    #[doc = "High Speed mode of operation"]
132    #[inline(always)]
133    pub fn is_high(&self) -> bool {
134        *self == SPEED_A::HIGH
135    }
136}
137#[doc = "Field `SPEED` writer - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.  
138
139 This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.  
140
141 1: standard mode (100 kbit/s)  
142
143 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)  
144
145 3: high speed mode (3.4 Mbit/s)  
146
147 Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
148pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SPEED_A>;
149impl<'a, REG> SPEED_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152    REG::Ux: From<u8>,
153{
154    #[doc = "Standard Speed mode of operation"]
155    #[inline(always)]
156    pub fn standard(self) -> &'a mut crate::W<REG> {
157        self.variant(SPEED_A::STANDARD)
158    }
159    #[doc = "Fast or Fast Plus mode of operation"]
160    #[inline(always)]
161    pub fn fast(self) -> &'a mut crate::W<REG> {
162        self.variant(SPEED_A::FAST)
163    }
164    #[doc = "High Speed mode of operation"]
165    #[inline(always)]
166    pub fn high(self) -> &'a mut crate::W<REG> {
167        self.variant(SPEED_A::HIGH)
168    }
169}
170#[doc = "Field `IC_10BITADDR_SLAVE` reader - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."]
171pub type IC_10BITADDR_SLAVE_R = crate::BitReader<IC_10BITADDR_SLAVE_A>;
172#[doc = "When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.  
173
174Value on reset: 0"]
175#[derive(Clone, Copy, Debug, PartialEq, Eq)]
176pub enum IC_10BITADDR_SLAVE_A {
177    #[doc = "0: Slave 7Bit addressing"]
178    ADDR_7BITS = 0,
179    #[doc = "1: Slave 10Bit addressing"]
180    ADDR_10BITS = 1,
181}
182impl From<IC_10BITADDR_SLAVE_A> for bool {
183    #[inline(always)]
184    fn from(variant: IC_10BITADDR_SLAVE_A) -> Self {
185        variant as u8 != 0
186    }
187}
188impl IC_10BITADDR_SLAVE_R {
189    #[doc = "Get enumerated values variant"]
190    #[inline(always)]
191    pub const fn variant(&self) -> IC_10BITADDR_SLAVE_A {
192        match self.bits {
193            false => IC_10BITADDR_SLAVE_A::ADDR_7BITS,
194            true => IC_10BITADDR_SLAVE_A::ADDR_10BITS,
195        }
196    }
197    #[doc = "Slave 7Bit addressing"]
198    #[inline(always)]
199    pub fn is_addr_7bits(&self) -> bool {
200        *self == IC_10BITADDR_SLAVE_A::ADDR_7BITS
201    }
202    #[doc = "Slave 10Bit addressing"]
203    #[inline(always)]
204    pub fn is_addr_10bits(&self) -> bool {
205        *self == IC_10BITADDR_SLAVE_A::ADDR_10BITS
206    }
207}
208#[doc = "Field `IC_10BITADDR_SLAVE` writer - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."]
209pub type IC_10BITADDR_SLAVE_W<'a, REG> = crate::BitWriter<'a, REG, IC_10BITADDR_SLAVE_A>;
210impl<'a, REG> IC_10BITADDR_SLAVE_W<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213{
214    #[doc = "Slave 7Bit addressing"]
215    #[inline(always)]
216    pub fn addr_7bits(self) -> &'a mut crate::W<REG> {
217        self.variant(IC_10BITADDR_SLAVE_A::ADDR_7BITS)
218    }
219    #[doc = "Slave 10Bit addressing"]
220    #[inline(always)]
221    pub fn addr_10bits(self) -> &'a mut crate::W<REG> {
222        self.variant(IC_10BITADDR_SLAVE_A::ADDR_10BITS)
223    }
224}
225#[doc = "Field `IC_10BITADDR_MASTER` reader - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"]
226pub type IC_10BITADDR_MASTER_R = crate::BitReader<IC_10BITADDR_MASTER_A>;
227#[doc = "Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing  
228
229Value on reset: 0"]
230#[derive(Clone, Copy, Debug, PartialEq, Eq)]
231pub enum IC_10BITADDR_MASTER_A {
232    #[doc = "0: Master 7Bit addressing mode"]
233    ADDR_7BITS = 0,
234    #[doc = "1: Master 10Bit addressing mode"]
235    ADDR_10BITS = 1,
236}
237impl From<IC_10BITADDR_MASTER_A> for bool {
238    #[inline(always)]
239    fn from(variant: IC_10BITADDR_MASTER_A) -> Self {
240        variant as u8 != 0
241    }
242}
243impl IC_10BITADDR_MASTER_R {
244    #[doc = "Get enumerated values variant"]
245    #[inline(always)]
246    pub const fn variant(&self) -> IC_10BITADDR_MASTER_A {
247        match self.bits {
248            false => IC_10BITADDR_MASTER_A::ADDR_7BITS,
249            true => IC_10BITADDR_MASTER_A::ADDR_10BITS,
250        }
251    }
252    #[doc = "Master 7Bit addressing mode"]
253    #[inline(always)]
254    pub fn is_addr_7bits(&self) -> bool {
255        *self == IC_10BITADDR_MASTER_A::ADDR_7BITS
256    }
257    #[doc = "Master 10Bit addressing mode"]
258    #[inline(always)]
259    pub fn is_addr_10bits(&self) -> bool {
260        *self == IC_10BITADDR_MASTER_A::ADDR_10BITS
261    }
262}
263#[doc = "Field `IC_10BITADDR_MASTER` writer - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"]
264pub type IC_10BITADDR_MASTER_W<'a, REG> = crate::BitWriter<'a, REG, IC_10BITADDR_MASTER_A>;
265impl<'a, REG> IC_10BITADDR_MASTER_W<'a, REG>
266where
267    REG: crate::Writable + crate::RegisterSpec,
268{
269    #[doc = "Master 7Bit addressing mode"]
270    #[inline(always)]
271    pub fn addr_7bits(self) -> &'a mut crate::W<REG> {
272        self.variant(IC_10BITADDR_MASTER_A::ADDR_7BITS)
273    }
274    #[doc = "Master 10Bit addressing mode"]
275    #[inline(always)]
276    pub fn addr_10bits(self) -> &'a mut crate::W<REG> {
277        self.variant(IC_10BITADDR_MASTER_A::ADDR_10BITS)
278    }
279}
280#[doc = "Field `IC_RESTART_EN` reader - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.  
281
282 Reset value: ENABLED"]
283pub type IC_RESTART_EN_R = crate::BitReader<IC_RESTART_EN_A>;
284#[doc = "Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.  
285
286 Reset value: ENABLED  
287
288Value on reset: 1"]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum IC_RESTART_EN_A {
291    #[doc = "0: Master restart disabled"]
292    DISABLED = 0,
293    #[doc = "1: Master restart enabled"]
294    ENABLED = 1,
295}
296impl From<IC_RESTART_EN_A> for bool {
297    #[inline(always)]
298    fn from(variant: IC_RESTART_EN_A) -> Self {
299        variant as u8 != 0
300    }
301}
302impl IC_RESTART_EN_R {
303    #[doc = "Get enumerated values variant"]
304    #[inline(always)]
305    pub const fn variant(&self) -> IC_RESTART_EN_A {
306        match self.bits {
307            false => IC_RESTART_EN_A::DISABLED,
308            true => IC_RESTART_EN_A::ENABLED,
309        }
310    }
311    #[doc = "Master restart disabled"]
312    #[inline(always)]
313    pub fn is_disabled(&self) -> bool {
314        *self == IC_RESTART_EN_A::DISABLED
315    }
316    #[doc = "Master restart enabled"]
317    #[inline(always)]
318    pub fn is_enabled(&self) -> bool {
319        *self == IC_RESTART_EN_A::ENABLED
320    }
321}
322#[doc = "Field `IC_RESTART_EN` writer - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.  
323
324 Reset value: ENABLED"]
325pub type IC_RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG, IC_RESTART_EN_A>;
326impl<'a, REG> IC_RESTART_EN_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    #[doc = "Master restart disabled"]
331    #[inline(always)]
332    pub fn disabled(self) -> &'a mut crate::W<REG> {
333        self.variant(IC_RESTART_EN_A::DISABLED)
334    }
335    #[doc = "Master restart enabled"]
336    #[inline(always)]
337    pub fn enabled(self) -> &'a mut crate::W<REG> {
338        self.variant(IC_RESTART_EN_A::ENABLED)
339    }
340}
341#[doc = "Field `IC_SLAVE_DISABLE` reader - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.  
342
343 If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.  
344
345 NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."]
346pub type IC_SLAVE_DISABLE_R = crate::BitReader<IC_SLAVE_DISABLE_A>;
347#[doc = "This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.  
348
349 If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.  
350
351 NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.  
352
353Value on reset: 1"]
354#[derive(Clone, Copy, Debug, PartialEq, Eq)]
355pub enum IC_SLAVE_DISABLE_A {
356    #[doc = "0: Slave mode is enabled"]
357    SLAVE_ENABLED = 0,
358    #[doc = "1: Slave mode is disabled"]
359    SLAVE_DISABLED = 1,
360}
361impl From<IC_SLAVE_DISABLE_A> for bool {
362    #[inline(always)]
363    fn from(variant: IC_SLAVE_DISABLE_A) -> Self {
364        variant as u8 != 0
365    }
366}
367impl IC_SLAVE_DISABLE_R {
368    #[doc = "Get enumerated values variant"]
369    #[inline(always)]
370    pub const fn variant(&self) -> IC_SLAVE_DISABLE_A {
371        match self.bits {
372            false => IC_SLAVE_DISABLE_A::SLAVE_ENABLED,
373            true => IC_SLAVE_DISABLE_A::SLAVE_DISABLED,
374        }
375    }
376    #[doc = "Slave mode is enabled"]
377    #[inline(always)]
378    pub fn is_slave_enabled(&self) -> bool {
379        *self == IC_SLAVE_DISABLE_A::SLAVE_ENABLED
380    }
381    #[doc = "Slave mode is disabled"]
382    #[inline(always)]
383    pub fn is_slave_disabled(&self) -> bool {
384        *self == IC_SLAVE_DISABLE_A::SLAVE_DISABLED
385    }
386}
387#[doc = "Field `IC_SLAVE_DISABLE` writer - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.  
388
389 If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.  
390
391 NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."]
392pub type IC_SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG, IC_SLAVE_DISABLE_A>;
393impl<'a, REG> IC_SLAVE_DISABLE_W<'a, REG>
394where
395    REG: crate::Writable + crate::RegisterSpec,
396{
397    #[doc = "Slave mode is enabled"]
398    #[inline(always)]
399    pub fn slave_enabled(self) -> &'a mut crate::W<REG> {
400        self.variant(IC_SLAVE_DISABLE_A::SLAVE_ENABLED)
401    }
402    #[doc = "Slave mode is disabled"]
403    #[inline(always)]
404    pub fn slave_disabled(self) -> &'a mut crate::W<REG> {
405        self.variant(IC_SLAVE_DISABLE_A::SLAVE_DISABLED)
406    }
407}
408#[doc = "Field `STOP_DET_IFADDRESSED` reader - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0  
409
410 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."]
411pub type STOP_DET_IFADDRESSED_R = crate::BitReader<STOP_DET_IFADDRESSED_A>;
412#[doc = "In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0  
413
414 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).  
415
416Value on reset: 0"]
417#[derive(Clone, Copy, Debug, PartialEq, Eq)]
418pub enum STOP_DET_IFADDRESSED_A {
419    #[doc = "0: slave issues STOP_DET intr always"]
420    DISABLED = 0,
421    #[doc = "1: slave issues STOP_DET intr only if addressed"]
422    ENABLED = 1,
423}
424impl From<STOP_DET_IFADDRESSED_A> for bool {
425    #[inline(always)]
426    fn from(variant: STOP_DET_IFADDRESSED_A) -> Self {
427        variant as u8 != 0
428    }
429}
430impl STOP_DET_IFADDRESSED_R {
431    #[doc = "Get enumerated values variant"]
432    #[inline(always)]
433    pub const fn variant(&self) -> STOP_DET_IFADDRESSED_A {
434        match self.bits {
435            false => STOP_DET_IFADDRESSED_A::DISABLED,
436            true => STOP_DET_IFADDRESSED_A::ENABLED,
437        }
438    }
439    #[doc = "slave issues STOP_DET intr always"]
440    #[inline(always)]
441    pub fn is_disabled(&self) -> bool {
442        *self == STOP_DET_IFADDRESSED_A::DISABLED
443    }
444    #[doc = "slave issues STOP_DET intr only if addressed"]
445    #[inline(always)]
446    pub fn is_enabled(&self) -> bool {
447        *self == STOP_DET_IFADDRESSED_A::ENABLED
448    }
449}
450#[doc = "Field `STOP_DET_IFADDRESSED` writer - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0  
451
452 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."]
453pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG, STOP_DET_IFADDRESSED_A>;
454impl<'a, REG> STOP_DET_IFADDRESSED_W<'a, REG>
455where
456    REG: crate::Writable + crate::RegisterSpec,
457{
458    #[doc = "slave issues STOP_DET intr always"]
459    #[inline(always)]
460    pub fn disabled(self) -> &'a mut crate::W<REG> {
461        self.variant(STOP_DET_IFADDRESSED_A::DISABLED)
462    }
463    #[doc = "slave issues STOP_DET intr only if addressed"]
464    #[inline(always)]
465    pub fn enabled(self) -> &'a mut crate::W<REG> {
466        self.variant(STOP_DET_IFADDRESSED_A::ENABLED)
467    }
468}
469#[doc = "Field `TX_EMPTY_CTRL` reader - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.  
470
471 Reset value: 0x0."]
472pub type TX_EMPTY_CTRL_R = crate::BitReader<TX_EMPTY_CTRL_A>;
473#[doc = "This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.  
474
475 Reset value: 0x0.  
476
477Value on reset: 0"]
478#[derive(Clone, Copy, Debug, PartialEq, Eq)]
479pub enum TX_EMPTY_CTRL_A {
480    #[doc = "0: Default behaviour of TX_EMPTY interrupt"]
481    DISABLED = 0,
482    #[doc = "1: Controlled generation of TX_EMPTY interrupt"]
483    ENABLED = 1,
484}
485impl From<TX_EMPTY_CTRL_A> for bool {
486    #[inline(always)]
487    fn from(variant: TX_EMPTY_CTRL_A) -> Self {
488        variant as u8 != 0
489    }
490}
491impl TX_EMPTY_CTRL_R {
492    #[doc = "Get enumerated values variant"]
493    #[inline(always)]
494    pub const fn variant(&self) -> TX_EMPTY_CTRL_A {
495        match self.bits {
496            false => TX_EMPTY_CTRL_A::DISABLED,
497            true => TX_EMPTY_CTRL_A::ENABLED,
498        }
499    }
500    #[doc = "Default behaviour of TX_EMPTY interrupt"]
501    #[inline(always)]
502    pub fn is_disabled(&self) -> bool {
503        *self == TX_EMPTY_CTRL_A::DISABLED
504    }
505    #[doc = "Controlled generation of TX_EMPTY interrupt"]
506    #[inline(always)]
507    pub fn is_enabled(&self) -> bool {
508        *self == TX_EMPTY_CTRL_A::ENABLED
509    }
510}
511#[doc = "Field `TX_EMPTY_CTRL` writer - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.  
512
513 Reset value: 0x0."]
514pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, TX_EMPTY_CTRL_A>;
515impl<'a, REG> TX_EMPTY_CTRL_W<'a, REG>
516where
517    REG: crate::Writable + crate::RegisterSpec,
518{
519    #[doc = "Default behaviour of TX_EMPTY interrupt"]
520    #[inline(always)]
521    pub fn disabled(self) -> &'a mut crate::W<REG> {
522        self.variant(TX_EMPTY_CTRL_A::DISABLED)
523    }
524    #[doc = "Controlled generation of TX_EMPTY interrupt"]
525    #[inline(always)]
526    pub fn enabled(self) -> &'a mut crate::W<REG> {
527        self.variant(TX_EMPTY_CTRL_A::ENABLED)
528    }
529}
530#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` reader - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.  
531
532 Reset value: 0x0."]
533pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader<RX_FIFO_FULL_HLD_CTRL_A>;
534#[doc = "This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.  
535
536 Reset value: 0x0.  
537
538Value on reset: 0"]
539#[derive(Clone, Copy, Debug, PartialEq, Eq)]
540pub enum RX_FIFO_FULL_HLD_CTRL_A {
541    #[doc = "0: Overflow when RX_FIFO is full"]
542    DISABLED = 0,
543    #[doc = "1: Hold bus when RX_FIFO is full"]
544    ENABLED = 1,
545}
546impl From<RX_FIFO_FULL_HLD_CTRL_A> for bool {
547    #[inline(always)]
548    fn from(variant: RX_FIFO_FULL_HLD_CTRL_A) -> Self {
549        variant as u8 != 0
550    }
551}
552impl RX_FIFO_FULL_HLD_CTRL_R {
553    #[doc = "Get enumerated values variant"]
554    #[inline(always)]
555    pub const fn variant(&self) -> RX_FIFO_FULL_HLD_CTRL_A {
556        match self.bits {
557            false => RX_FIFO_FULL_HLD_CTRL_A::DISABLED,
558            true => RX_FIFO_FULL_HLD_CTRL_A::ENABLED,
559        }
560    }
561    #[doc = "Overflow when RX_FIFO is full"]
562    #[inline(always)]
563    pub fn is_disabled(&self) -> bool {
564        *self == RX_FIFO_FULL_HLD_CTRL_A::DISABLED
565    }
566    #[doc = "Hold bus when RX_FIFO is full"]
567    #[inline(always)]
568    pub fn is_enabled(&self) -> bool {
569        *self == RX_FIFO_FULL_HLD_CTRL_A::ENABLED
570    }
571}
572#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` writer - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.  
573
574 Reset value: 0x0."]
575pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, RX_FIFO_FULL_HLD_CTRL_A>;
576impl<'a, REG> RX_FIFO_FULL_HLD_CTRL_W<'a, REG>
577where
578    REG: crate::Writable + crate::RegisterSpec,
579{
580    #[doc = "Overflow when RX_FIFO is full"]
581    #[inline(always)]
582    pub fn disabled(self) -> &'a mut crate::W<REG> {
583        self.variant(RX_FIFO_FULL_HLD_CTRL_A::DISABLED)
584    }
585    #[doc = "Hold bus when RX_FIFO is full"]
586    #[inline(always)]
587    pub fn enabled(self) -> &'a mut crate::W<REG> {
588        self.variant(RX_FIFO_FULL_HLD_CTRL_A::ENABLED)
589    }
590}
591#[doc = "Field `STOP_DET_IF_MASTER_ACTIVE` reader - Master issues the STOP_DET interrupt irrespective of whether master is active or not"]
592pub type STOP_DET_IF_MASTER_ACTIVE_R = crate::BitReader;
593impl R {
594    #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled.  
595
596 NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."]
597    #[inline(always)]
598    pub fn master_mode(&self) -> MASTER_MODE_R {
599        MASTER_MODE_R::new((self.bits & 1) != 0)
600    }
601    #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.  
602
603 This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.  
604
605 1: standard mode (100 kbit/s)  
606
607 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)  
608
609 3: high speed mode (3.4 Mbit/s)  
610
611 Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
612    #[inline(always)]
613    pub fn speed(&self) -> SPEED_R {
614        SPEED_R::new(((self.bits >> 1) & 3) as u8)
615    }
616    #[doc = "Bit 3 - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."]
617    #[inline(always)]
618    pub fn ic_10bitaddr_slave(&self) -> IC_10BITADDR_SLAVE_R {
619        IC_10BITADDR_SLAVE_R::new(((self.bits >> 3) & 1) != 0)
620    }
621    #[doc = "Bit 4 - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"]
622    #[inline(always)]
623    pub fn ic_10bitaddr_master(&self) -> IC_10BITADDR_MASTER_R {
624        IC_10BITADDR_MASTER_R::new(((self.bits >> 4) & 1) != 0)
625    }
626    #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.  
627
628 Reset value: ENABLED"]
629    #[inline(always)]
630    pub fn ic_restart_en(&self) -> IC_RESTART_EN_R {
631        IC_RESTART_EN_R::new(((self.bits >> 5) & 1) != 0)
632    }
633    #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.  
634
635 If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.  
636
637 NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."]
638    #[inline(always)]
639    pub fn ic_slave_disable(&self) -> IC_SLAVE_DISABLE_R {
640        IC_SLAVE_DISABLE_R::new(((self.bits >> 6) & 1) != 0)
641    }
642    #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0  
643
644 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."]
645    #[inline(always)]
646    pub fn stop_det_ifaddressed(&self) -> STOP_DET_IFADDRESSED_R {
647        STOP_DET_IFADDRESSED_R::new(((self.bits >> 7) & 1) != 0)
648    }
649    #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.  
650
651 Reset value: 0x0."]
652    #[inline(always)]
653    pub fn tx_empty_ctrl(&self) -> TX_EMPTY_CTRL_R {
654        TX_EMPTY_CTRL_R::new(((self.bits >> 8) & 1) != 0)
655    }
656    #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.  
657
658 Reset value: 0x0."]
659    #[inline(always)]
660    pub fn rx_fifo_full_hld_ctrl(&self) -> RX_FIFO_FULL_HLD_CTRL_R {
661        RX_FIFO_FULL_HLD_CTRL_R::new(((self.bits >> 9) & 1) != 0)
662    }
663    #[doc = "Bit 10 - Master issues the STOP_DET interrupt irrespective of whether master is active or not"]
664    #[inline(always)]
665    pub fn stop_det_if_master_active(&self) -> STOP_DET_IF_MASTER_ACTIVE_R {
666        STOP_DET_IF_MASTER_ACTIVE_R::new(((self.bits >> 10) & 1) != 0)
667    }
668}
669impl W {
670    #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled.  
671
672 NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."]
673    #[inline(always)]
674    #[must_use]
675    pub fn master_mode(&mut self) -> MASTER_MODE_W<IC_CON_SPEC> {
676        MASTER_MODE_W::new(self, 0)
677    }
678    #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.  
679
680 This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.  
681
682 1: standard mode (100 kbit/s)  
683
684 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)  
685
686 3: high speed mode (3.4 Mbit/s)  
687
688 Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
689    #[inline(always)]
690    #[must_use]
691    pub fn speed(&mut self) -> SPEED_W<IC_CON_SPEC> {
692        SPEED_W::new(self, 1)
693    }
694    #[doc = "Bit 3 - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."]
695    #[inline(always)]
696    #[must_use]
697    pub fn ic_10bitaddr_slave(&mut self) -> IC_10BITADDR_SLAVE_W<IC_CON_SPEC> {
698        IC_10BITADDR_SLAVE_W::new(self, 3)
699    }
700    #[doc = "Bit 4 - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"]
701    #[inline(always)]
702    #[must_use]
703    pub fn ic_10bitaddr_master(&mut self) -> IC_10BITADDR_MASTER_W<IC_CON_SPEC> {
704        IC_10BITADDR_MASTER_W::new(self, 4)
705    }
706    #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.  
707
708 Reset value: ENABLED"]
709    #[inline(always)]
710    #[must_use]
711    pub fn ic_restart_en(&mut self) -> IC_RESTART_EN_W<IC_CON_SPEC> {
712        IC_RESTART_EN_W::new(self, 5)
713    }
714    #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.  
715
716 If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.  
717
718 NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."]
719    #[inline(always)]
720    #[must_use]
721    pub fn ic_slave_disable(&mut self) -> IC_SLAVE_DISABLE_W<IC_CON_SPEC> {
722        IC_SLAVE_DISABLE_W::new(self, 6)
723    }
724    #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0  
725
726 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."]
727    #[inline(always)]
728    #[must_use]
729    pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W<IC_CON_SPEC> {
730        STOP_DET_IFADDRESSED_W::new(self, 7)
731    }
732    #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.  
733
734 Reset value: 0x0."]
735    #[inline(always)]
736    #[must_use]
737    pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W<IC_CON_SPEC> {
738        TX_EMPTY_CTRL_W::new(self, 8)
739    }
740    #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.  
741
742 Reset value: 0x0."]
743    #[inline(always)]
744    #[must_use]
745    pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W<IC_CON_SPEC> {
746        RX_FIFO_FULL_HLD_CTRL_W::new(self, 9)
747    }
748    #[doc = r" Writes raw bits to the register."]
749    #[doc = r""]
750    #[doc = r" # Safety"]
751    #[doc = r""]
752    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
753    #[inline(always)]
754    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
755        self.bits = bits;
756        self
757    }
758}
759#[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\]
760register being set to 0. Writes at other times have no effect.  
761
762 Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.  
763
764You can [`read`](crate::generic::Reg::read) this register and get [`ic_con::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_con::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
765pub struct IC_CON_SPEC;
766impl crate::RegisterSpec for IC_CON_SPEC {
767    type Ux = u32;
768}
769#[doc = "`read()` method returns [`ic_con::R`](R) reader structure"]
770impl crate::Readable for IC_CON_SPEC {}
771#[doc = "`write(|w| ..)` method takes [`ic_con::W`](W) writer structure"]
772impl crate::Writable for IC_CON_SPEC {
773    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
774    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
775}
776#[doc = "`reset()` method sets IC_CON to value 0x65"]
777impl crate::Resettable for IC_CON_SPEC {
778    const RESET_VALUE: u32 = 0x65;
779}
rp2040_pac/i2c0/ic_con.rs

rp2040_pac/i2c0/
ic_con.rs
