rp2040_pac/
dma.rs

Help
1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    ch: [CH; 12],
5    _reserved1: [u8; 0x0100],
6    intr: INTR,
7    inte0: INTE0,
8    intf0: INTF0,
9    ints0: INTS0,
10    _reserved5: [u8; 0x04],
11    inte1: INTE1,
12    intf1: INTF1,
13    ints1: INTS1,
14    timer0: TIMER0,
15    timer1: TIMER1,
16    timer2: TIMER2,
17    timer3: TIMER3,
18    multi_chan_trigger: MULTI_CHAN_TRIGGER,
19    sniff_ctrl: SNIFF_CTRL,
20    sniff_data: SNIFF_DATA,
21    _reserved15: [u8; 0x04],
22    fifo_levels: FIFO_LEVELS,
23    chan_abort: CHAN_ABORT,
24    n_channels: N_CHANNELS,
25    _reserved18: [u8; 0x03b4],
26    ch0_dbg_ctdreq: CH0_DBG_CTDREQ,
27    ch0_dbg_tcr: CH0_DBG_TCR,
28    _reserved20: [u8; 0x38],
29    ch1_dbg_ctdreq: CH1_DBG_CTDREQ,
30    ch1_dbg_tcr: CH1_DBG_TCR,
31    _reserved22: [u8; 0x38],
32    ch2_dbg_ctdreq: CH2_DBG_CTDREQ,
33    ch2_dbg_tcr: CH2_DBG_TCR,
34    _reserved24: [u8; 0x38],
35    ch3_dbg_ctdreq: CH3_DBG_CTDREQ,
36    ch3_dbg_tcr: CH3_DBG_TCR,
37    _reserved26: [u8; 0x38],
38    ch4_dbg_ctdreq: CH4_DBG_CTDREQ,
39    ch4_dbg_tcr: CH4_DBG_TCR,
40    _reserved28: [u8; 0x38],
41    ch5_dbg_ctdreq: CH5_DBG_CTDREQ,
42    ch5_dbg_tcr: CH5_DBG_TCR,
43    _reserved30: [u8; 0x38],
44    ch6_dbg_ctdreq: CH6_DBG_CTDREQ,
45    ch6_dbg_tcr: CH6_DBG_TCR,
46    _reserved32: [u8; 0x38],
47    ch7_dbg_ctdreq: CH7_DBG_CTDREQ,
48    ch7_dbg_tcr: CH7_DBG_TCR,
49    _reserved34: [u8; 0x38],
50    ch8_dbg_ctdreq: CH8_DBG_CTDREQ,
51    ch8_dbg_tcr: CH8_DBG_TCR,
52    _reserved36: [u8; 0x38],
53    ch9_dbg_ctdreq: CH9_DBG_CTDREQ,
54    ch9_dbg_tcr: CH9_DBG_TCR,
55    _reserved38: [u8; 0x38],
56    ch10_dbg_ctdreq: CH10_DBG_CTDREQ,
57    ch10_dbg_tcr: CH10_DBG_TCR,
58    _reserved40: [u8; 0x38],
59    ch11_dbg_ctdreq: CH11_DBG_CTDREQ,
60    ch11_dbg_tcr: CH11_DBG_TCR,
61}
62impl RegisterBlock {
63    #[doc = "0x00..0x300 - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"]
64    #[inline(always)]
65    pub const fn ch(&self, n: usize) -> &CH {
66        &self.ch[n]
67    }
68    #[doc = "Iterator for array of:"]
69    #[doc = "0x00..0x300 - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"]
70    #[inline(always)]
71    pub fn ch_iter(&self) -> impl Iterator<Item = &CH> {
72        self.ch.iter()
73    }
74    #[doc = "0x400 - Interrupt Status (raw)"]
75    #[inline(always)]
76    pub const fn intr(&self) -> &INTR {
77        &self.intr
78    }
79    #[doc = "0x404 - Interrupt Enables for IRQ 0"]
80    #[inline(always)]
81    pub const fn inte0(&self) -> &INTE0 {
82        &self.inte0
83    }
84    #[doc = "0x408 - Force Interrupts"]
85    #[inline(always)]
86    pub const fn intf0(&self) -> &INTF0 {
87        &self.intf0
88    }
89    #[doc = "0x40c - Interrupt Status for IRQ 0"]
90    #[inline(always)]
91    pub const fn ints0(&self) -> &INTS0 {
92        &self.ints0
93    }
94    #[doc = "0x414 - Interrupt Enables for IRQ 1"]
95    #[inline(always)]
96    pub const fn inte1(&self) -> &INTE1 {
97        &self.inte1
98    }
99    #[doc = "0x418 - Force Interrupts for IRQ 1"]
100    #[inline(always)]
101    pub const fn intf1(&self) -> &INTF1 {
102        &self.intf1
103    }
104    #[doc = "0x41c - Interrupt Status (masked) for IRQ 1"]
105    #[inline(always)]
106    pub const fn ints1(&self) -> &INTS1 {
107        &self.ints1
108    }
109    #[doc = "0x420 - Pacing (X/Y) Fractional Timer  
110 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
111    #[inline(always)]
112    pub const fn timer0(&self) -> &TIMER0 {
113        &self.timer0
114    }
115    #[doc = "0x424 - Pacing (X/Y) Fractional Timer  
116 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
117    #[inline(always)]
118    pub const fn timer1(&self) -> &TIMER1 {
119        &self.timer1
120    }
121    #[doc = "0x428 - Pacing (X/Y) Fractional Timer  
122 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
123    #[inline(always)]
124    pub const fn timer2(&self) -> &TIMER2 {
125        &self.timer2
126    }
127    #[doc = "0x42c - Pacing (X/Y) Fractional Timer  
128 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
129    #[inline(always)]
130    pub const fn timer3(&self) -> &TIMER3 {
131        &self.timer3
132    }
133    #[doc = "0x430 - Trigger one or more channels simultaneously"]
134    #[inline(always)]
135    pub const fn multi_chan_trigger(&self) -> &MULTI_CHAN_TRIGGER {
136        &self.multi_chan_trigger
137    }
138    #[doc = "0x434 - Sniffer Control"]
139    #[inline(always)]
140    pub const fn sniff_ctrl(&self) -> &SNIFF_CTRL {
141        &self.sniff_ctrl
142    }
143    #[doc = "0x438 - Data accumulator for sniff hardware  
144 Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."]
145    #[inline(always)]
146    pub const fn sniff_data(&self) -> &SNIFF_DATA {
147        &self.sniff_data
148    }
149    #[doc = "0x440 - Debug RAF, WAF, TDF levels"]
150    #[inline(always)]
151    pub const fn fifo_levels(&self) -> &FIFO_LEVELS {
152        &self.fifo_levels
153    }
154    #[doc = "0x444 - Abort an in-progress transfer sequence on one or more channels"]
155    #[inline(always)]
156    pub const fn chan_abort(&self) -> &CHAN_ABORT {
157        &self.chan_abort
158    }
159    #[doc = "0x448 - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."]
160    #[inline(always)]
161    pub const fn n_channels(&self) -> &N_CHANNELS {
162        &self.n_channels
163    }
164    #[doc = "0x800 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
165    #[inline(always)]
166    pub const fn ch0_dbg_ctdreq(&self) -> &CH0_DBG_CTDREQ {
167        &self.ch0_dbg_ctdreq
168    }
169    #[doc = "0x804 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
170    #[inline(always)]
171    pub const fn ch0_dbg_tcr(&self) -> &CH0_DBG_TCR {
172        &self.ch0_dbg_tcr
173    }
174    #[doc = "0x840 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
175    #[inline(always)]
176    pub const fn ch1_dbg_ctdreq(&self) -> &CH1_DBG_CTDREQ {
177        &self.ch1_dbg_ctdreq
178    }
179    #[doc = "0x844 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
180    #[inline(always)]
181    pub const fn ch1_dbg_tcr(&self) -> &CH1_DBG_TCR {
182        &self.ch1_dbg_tcr
183    }
184    #[doc = "0x880 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
185    #[inline(always)]
186    pub const fn ch2_dbg_ctdreq(&self) -> &CH2_DBG_CTDREQ {
187        &self.ch2_dbg_ctdreq
188    }
189    #[doc = "0x884 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
190    #[inline(always)]
191    pub const fn ch2_dbg_tcr(&self) -> &CH2_DBG_TCR {
192        &self.ch2_dbg_tcr
193    }
194    #[doc = "0x8c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
195    #[inline(always)]
196    pub const fn ch3_dbg_ctdreq(&self) -> &CH3_DBG_CTDREQ {
197        &self.ch3_dbg_ctdreq
198    }
199    #[doc = "0x8c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
200    #[inline(always)]
201    pub const fn ch3_dbg_tcr(&self) -> &CH3_DBG_TCR {
202        &self.ch3_dbg_tcr
203    }
204    #[doc = "0x900 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
205    #[inline(always)]
206    pub const fn ch4_dbg_ctdreq(&self) -> &CH4_DBG_CTDREQ {
207        &self.ch4_dbg_ctdreq
208    }
209    #[doc = "0x904 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
210    #[inline(always)]
211    pub const fn ch4_dbg_tcr(&self) -> &CH4_DBG_TCR {
212        &self.ch4_dbg_tcr
213    }
214    #[doc = "0x940 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
215    #[inline(always)]
216    pub const fn ch5_dbg_ctdreq(&self) -> &CH5_DBG_CTDREQ {
217        &self.ch5_dbg_ctdreq
218    }
219    #[doc = "0x944 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
220    #[inline(always)]
221    pub const fn ch5_dbg_tcr(&self) -> &CH5_DBG_TCR {
222        &self.ch5_dbg_tcr
223    }
224    #[doc = "0x980 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
225    #[inline(always)]
226    pub const fn ch6_dbg_ctdreq(&self) -> &CH6_DBG_CTDREQ {
227        &self.ch6_dbg_ctdreq
228    }
229    #[doc = "0x984 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
230    #[inline(always)]
231    pub const fn ch6_dbg_tcr(&self) -> &CH6_DBG_TCR {
232        &self.ch6_dbg_tcr
233    }
234    #[doc = "0x9c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
235    #[inline(always)]
236    pub const fn ch7_dbg_ctdreq(&self) -> &CH7_DBG_CTDREQ {
237        &self.ch7_dbg_ctdreq
238    }
239    #[doc = "0x9c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
240    #[inline(always)]
241    pub const fn ch7_dbg_tcr(&self) -> &CH7_DBG_TCR {
242        &self.ch7_dbg_tcr
243    }
244    #[doc = "0xa00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
245    #[inline(always)]
246    pub const fn ch8_dbg_ctdreq(&self) -> &CH8_DBG_CTDREQ {
247        &self.ch8_dbg_ctdreq
248    }
249    #[doc = "0xa04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
250    #[inline(always)]
251    pub const fn ch8_dbg_tcr(&self) -> &CH8_DBG_TCR {
252        &self.ch8_dbg_tcr
253    }
254    #[doc = "0xa40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
255    #[inline(always)]
256    pub const fn ch9_dbg_ctdreq(&self) -> &CH9_DBG_CTDREQ {
257        &self.ch9_dbg_ctdreq
258    }
259    #[doc = "0xa44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
260    #[inline(always)]
261    pub const fn ch9_dbg_tcr(&self) -> &CH9_DBG_TCR {
262        &self.ch9_dbg_tcr
263    }
264    #[doc = "0xa80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
265    #[inline(always)]
266    pub const fn ch10_dbg_ctdreq(&self) -> &CH10_DBG_CTDREQ {
267        &self.ch10_dbg_ctdreq
268    }
269    #[doc = "0xa84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
270    #[inline(always)]
271    pub const fn ch10_dbg_tcr(&self) -> &CH10_DBG_TCR {
272        &self.ch10_dbg_tcr
273    }
274    #[doc = "0xac0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
275    #[inline(always)]
276    pub const fn ch11_dbg_ctdreq(&self) -> &CH11_DBG_CTDREQ {
277        &self.ch11_dbg_ctdreq
278    }
279    #[doc = "0xac4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
280    #[inline(always)]
281    pub const fn ch11_dbg_tcr(&self) -> &CH11_DBG_TCR {
282        &self.ch11_dbg_tcr
283    }
284}
285#[doc = "Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"]
286pub use self::ch::CH;
287#[doc = r"Cluster"]
288#[doc = "Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"]
289pub mod ch;
290#[doc = "INTR (rw) register accessor: Interrupt Status (raw)  
291
292You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
293
294For information about available fields see [`mod@intr`]
295module"]
296pub type INTR = crate::Reg<intr::INTR_SPEC>;
297#[doc = "Interrupt Status (raw)"]
298pub mod intr;
299#[doc = "INTE0 (rw) register accessor: Interrupt Enables for IRQ 0  
300
301You can [`read`](crate::generic::Reg::read) this register and get [`inte0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
302
303For information about available fields see [`mod@inte0`]
304module"]
305pub type INTE0 = crate::Reg<inte0::INTE0_SPEC>;
306#[doc = "Interrupt Enables for IRQ 0"]
307pub mod inte0;
308#[doc = "INTF0 (rw) register accessor: Force Interrupts  
309
310You can [`read`](crate::generic::Reg::read) this register and get [`intf0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
311
312For information about available fields see [`mod@intf0`]
313module"]
314pub type INTF0 = crate::Reg<intf0::INTF0_SPEC>;
315#[doc = "Force Interrupts"]
316pub mod intf0;
317#[doc = "INTS0 (rw) register accessor: Interrupt Status for IRQ 0  
318
319You can [`read`](crate::generic::Reg::read) this register and get [`ints0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
320
321For information about available fields see [`mod@ints0`]
322module"]
323pub type INTS0 = crate::Reg<ints0::INTS0_SPEC>;
324#[doc = "Interrupt Status for IRQ 0"]
325pub mod ints0;
326#[doc = "INTE1 (rw) register accessor: Interrupt Enables for IRQ 1  
327
328You can [`read`](crate::generic::Reg::read) this register and get [`inte1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
329
330For information about available fields see [`mod@inte1`]
331module"]
332pub type INTE1 = crate::Reg<inte1::INTE1_SPEC>;
333#[doc = "Interrupt Enables for IRQ 1"]
334pub mod inte1;
335#[doc = "INTF1 (rw) register accessor: Force Interrupts for IRQ 1  
336
337You can [`read`](crate::generic::Reg::read) this register and get [`intf1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
338
339For information about available fields see [`mod@intf1`]
340module"]
341pub type INTF1 = crate::Reg<intf1::INTF1_SPEC>;
342#[doc = "Force Interrupts for IRQ 1"]
343pub mod intf1;
344#[doc = "INTS1 (rw) register accessor: Interrupt Status (masked) for IRQ 1  
345
346You can [`read`](crate::generic::Reg::read) this register and get [`ints1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
347
348For information about available fields see [`mod@ints1`]
349module"]
350pub type INTS1 = crate::Reg<ints1::INTS1_SPEC>;
351#[doc = "Interrupt Status (masked) for IRQ 1"]
352pub mod ints1;
353#[doc = "TIMER0 (rw) register accessor: Pacing (X/Y) Fractional Timer  
354 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
355
356You can [`read`](crate::generic::Reg::read) this register and get [`timer0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
357
358For information about available fields see [`mod@timer0`]
359module"]
360pub type TIMER0 = crate::Reg<timer0::TIMER0_SPEC>;
361#[doc = "Pacing (X/Y) Fractional Timer  
362 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
363pub mod timer0;
364#[doc = "TIMER1 (rw) register accessor: Pacing (X/Y) Fractional Timer  
365 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
366
367You can [`read`](crate::generic::Reg::read) this register and get [`timer1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
368
369For information about available fields see [`mod@timer1`]
370module"]
371pub type TIMER1 = crate::Reg<timer1::TIMER1_SPEC>;
372#[doc = "Pacing (X/Y) Fractional Timer  
373 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
374pub mod timer1;
375#[doc = "TIMER2 (rw) register accessor: Pacing (X/Y) Fractional Timer  
376 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
377
378You can [`read`](crate::generic::Reg::read) this register and get [`timer2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
379
380For information about available fields see [`mod@timer2`]
381module"]
382pub type TIMER2 = crate::Reg<timer2::TIMER2_SPEC>;
383#[doc = "Pacing (X/Y) Fractional Timer  
384 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
385pub mod timer2;
386#[doc = "TIMER3 (rw) register accessor: Pacing (X/Y) Fractional Timer  
387 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
388
389You can [`read`](crate::generic::Reg::read) this register and get [`timer3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
390
391For information about available fields see [`mod@timer3`]
392module"]
393pub type TIMER3 = crate::Reg<timer3::TIMER3_SPEC>;
394#[doc = "Pacing (X/Y) Fractional Timer  
395 The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."]
396pub mod timer3;
397#[doc = "MULTI_CHAN_TRIGGER (rw) register accessor: Trigger one or more channels simultaneously  
398
399You can [`read`](crate::generic::Reg::read) this register and get [`multi_chan_trigger::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`multi_chan_trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
400
401For information about available fields see [`mod@multi_chan_trigger`]
402module"]
403pub type MULTI_CHAN_TRIGGER = crate::Reg<multi_chan_trigger::MULTI_CHAN_TRIGGER_SPEC>;
404#[doc = "Trigger one or more channels simultaneously"]
405pub mod multi_chan_trigger;
406#[doc = "SNIFF_CTRL (rw) register accessor: Sniffer Control  
407
408You can [`read`](crate::generic::Reg::read) this register and get [`sniff_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
409
410For information about available fields see [`mod@sniff_ctrl`]
411module"]
412pub type SNIFF_CTRL = crate::Reg<sniff_ctrl::SNIFF_CTRL_SPEC>;
413#[doc = "Sniffer Control"]
414pub mod sniff_ctrl;
415#[doc = "SNIFF_DATA (rw) register accessor: Data accumulator for sniff hardware  
416 Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.  
417
418You can [`read`](crate::generic::Reg::read) this register and get [`sniff_data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
419
420For information about available fields see [`mod@sniff_data`]
421module"]
422pub type SNIFF_DATA = crate::Reg<sniff_data::SNIFF_DATA_SPEC>;
423#[doc = "Data accumulator for sniff hardware  
424 Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."]
425pub mod sniff_data;
426#[doc = "FIFO_LEVELS (r) register accessor: Debug RAF, WAF, TDF levels  
427
428You can [`read`](crate::generic::Reg::read) this register and get [`fifo_levels::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
429
430For information about available fields see [`mod@fifo_levels`]
431module"]
432pub type FIFO_LEVELS = crate::Reg<fifo_levels::FIFO_LEVELS_SPEC>;
433#[doc = "Debug RAF, WAF, TDF levels"]
434pub mod fifo_levels;
435#[doc = "CHAN_ABORT (rw) register accessor: Abort an in-progress transfer sequence on one or more channels  
436
437You can [`read`](crate::generic::Reg::read) this register and get [`chan_abort::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chan_abort::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
438
439For information about available fields see [`mod@chan_abort`]
440module"]
441pub type CHAN_ABORT = crate::Reg<chan_abort::CHAN_ABORT_SPEC>;
442#[doc = "Abort an in-progress transfer sequence on one or more channels"]
443pub mod chan_abort;
444#[doc = "N_CHANNELS (r) register accessor: The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.  
445
446You can [`read`](crate::generic::Reg::read) this register and get [`n_channels::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
447
448For information about available fields see [`mod@n_channels`]
449module"]
450pub type N_CHANNELS = crate::Reg<n_channels::N_CHANNELS_SPEC>;
451#[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."]
452pub mod n_channels;
453#[doc = "CH0_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
454
455You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
456
457For information about available fields see [`mod@ch0_dbg_ctdreq`]
458module"]
459pub type CH0_DBG_CTDREQ = crate::Reg<ch0_dbg_ctdreq::CH0_DBG_CTDREQ_SPEC>;
460#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
461pub mod ch0_dbg_ctdreq;
462#[doc = "CH0_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
463
464You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
465
466For information about available fields see [`mod@ch0_dbg_tcr`]
467module"]
468pub type CH0_DBG_TCR = crate::Reg<ch0_dbg_tcr::CH0_DBG_TCR_SPEC>;
469#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
470pub mod ch0_dbg_tcr;
471#[doc = "CH1_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
472
473You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
474
475For information about available fields see [`mod@ch1_dbg_ctdreq`]
476module"]
477pub type CH1_DBG_CTDREQ = crate::Reg<ch1_dbg_ctdreq::CH1_DBG_CTDREQ_SPEC>;
478#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
479pub mod ch1_dbg_ctdreq;
480#[doc = "CH1_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
481
482You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
483
484For information about available fields see [`mod@ch1_dbg_tcr`]
485module"]
486pub type CH1_DBG_TCR = crate::Reg<ch1_dbg_tcr::CH1_DBG_TCR_SPEC>;
487#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
488pub mod ch1_dbg_tcr;
489#[doc = "CH2_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
490
491You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
492
493For information about available fields see [`mod@ch2_dbg_ctdreq`]
494module"]
495pub type CH2_DBG_CTDREQ = crate::Reg<ch2_dbg_ctdreq::CH2_DBG_CTDREQ_SPEC>;
496#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
497pub mod ch2_dbg_ctdreq;
498#[doc = "CH2_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
499
500You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
501
502For information about available fields see [`mod@ch2_dbg_tcr`]
503module"]
504pub type CH2_DBG_TCR = crate::Reg<ch2_dbg_tcr::CH2_DBG_TCR_SPEC>;
505#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
506pub mod ch2_dbg_tcr;
507#[doc = "CH3_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
508
509You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
510
511For information about available fields see [`mod@ch3_dbg_ctdreq`]
512module"]
513pub type CH3_DBG_CTDREQ = crate::Reg<ch3_dbg_ctdreq::CH3_DBG_CTDREQ_SPEC>;
514#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
515pub mod ch3_dbg_ctdreq;
516#[doc = "CH3_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
517
518You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
519
520For information about available fields see [`mod@ch3_dbg_tcr`]
521module"]
522pub type CH3_DBG_TCR = crate::Reg<ch3_dbg_tcr::CH3_DBG_TCR_SPEC>;
523#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
524pub mod ch3_dbg_tcr;
525#[doc = "CH4_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
526
527You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
528
529For information about available fields see [`mod@ch4_dbg_ctdreq`]
530module"]
531pub type CH4_DBG_CTDREQ = crate::Reg<ch4_dbg_ctdreq::CH4_DBG_CTDREQ_SPEC>;
532#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
533pub mod ch4_dbg_ctdreq;
534#[doc = "CH4_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
535
536You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
537
538For information about available fields see [`mod@ch4_dbg_tcr`]
539module"]
540pub type CH4_DBG_TCR = crate::Reg<ch4_dbg_tcr::CH4_DBG_TCR_SPEC>;
541#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
542pub mod ch4_dbg_tcr;
543#[doc = "CH5_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
544
545You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
546
547For information about available fields see [`mod@ch5_dbg_ctdreq`]
548module"]
549pub type CH5_DBG_CTDREQ = crate::Reg<ch5_dbg_ctdreq::CH5_DBG_CTDREQ_SPEC>;
550#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
551pub mod ch5_dbg_ctdreq;
552#[doc = "CH5_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
553
554You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
555
556For information about available fields see [`mod@ch5_dbg_tcr`]
557module"]
558pub type CH5_DBG_TCR = crate::Reg<ch5_dbg_tcr::CH5_DBG_TCR_SPEC>;
559#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
560pub mod ch5_dbg_tcr;
561#[doc = "CH6_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
562
563You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
564
565For information about available fields see [`mod@ch6_dbg_ctdreq`]
566module"]
567pub type CH6_DBG_CTDREQ = crate::Reg<ch6_dbg_ctdreq::CH6_DBG_CTDREQ_SPEC>;
568#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
569pub mod ch6_dbg_ctdreq;
570#[doc = "CH6_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
571
572You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
573
574For information about available fields see [`mod@ch6_dbg_tcr`]
575module"]
576pub type CH6_DBG_TCR = crate::Reg<ch6_dbg_tcr::CH6_DBG_TCR_SPEC>;
577#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
578pub mod ch6_dbg_tcr;
579#[doc = "CH7_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
580
581You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
582
583For information about available fields see [`mod@ch7_dbg_ctdreq`]
584module"]
585pub type CH7_DBG_CTDREQ = crate::Reg<ch7_dbg_ctdreq::CH7_DBG_CTDREQ_SPEC>;
586#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
587pub mod ch7_dbg_ctdreq;
588#[doc = "CH7_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
589
590You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
591
592For information about available fields see [`mod@ch7_dbg_tcr`]
593module"]
594pub type CH7_DBG_TCR = crate::Reg<ch7_dbg_tcr::CH7_DBG_TCR_SPEC>;
595#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
596pub mod ch7_dbg_tcr;
597#[doc = "CH8_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
598
599You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
600
601For information about available fields see [`mod@ch8_dbg_ctdreq`]
602module"]
603pub type CH8_DBG_CTDREQ = crate::Reg<ch8_dbg_ctdreq::CH8_DBG_CTDREQ_SPEC>;
604#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
605pub mod ch8_dbg_ctdreq;
606#[doc = "CH8_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
607
608You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
609
610For information about available fields see [`mod@ch8_dbg_tcr`]
611module"]
612pub type CH8_DBG_TCR = crate::Reg<ch8_dbg_tcr::CH8_DBG_TCR_SPEC>;
613#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
614pub mod ch8_dbg_tcr;
615#[doc = "CH9_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
616
617You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
618
619For information about available fields see [`mod@ch9_dbg_ctdreq`]
620module"]
621pub type CH9_DBG_CTDREQ = crate::Reg<ch9_dbg_ctdreq::CH9_DBG_CTDREQ_SPEC>;
622#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
623pub mod ch9_dbg_ctdreq;
624#[doc = "CH9_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
625
626You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
627
628For information about available fields see [`mod@ch9_dbg_tcr`]
629module"]
630pub type CH9_DBG_TCR = crate::Reg<ch9_dbg_tcr::CH9_DBG_TCR_SPEC>;
631#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
632pub mod ch9_dbg_tcr;
633#[doc = "CH10_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
634
635You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
636
637For information about available fields see [`mod@ch10_dbg_ctdreq`]
638module"]
639pub type CH10_DBG_CTDREQ = crate::Reg<ch10_dbg_ctdreq::CH10_DBG_CTDREQ_SPEC>;
640#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
641pub mod ch10_dbg_ctdreq;
642#[doc = "CH10_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
643
644You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
645
646For information about available fields see [`mod@ch10_dbg_tcr`]
647module"]
648pub type CH10_DBG_TCR = crate::Reg<ch10_dbg_tcr::CH10_DBG_TCR_SPEC>;
649#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
650pub mod ch10_dbg_tcr;
651#[doc = "CH11_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
652
653You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
654
655For information about available fields see [`mod@ch11_dbg_ctdreq`]
656module"]
657pub type CH11_DBG_CTDREQ = crate::Reg<ch11_dbg_ctdreq::CH11_DBG_CTDREQ_SPEC>;
658#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."]
659pub mod ch11_dbg_ctdreq;
660#[doc = "CH11_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
661
662You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
663
664For information about available fields see [`mod@ch11_dbg_tcr`]
665module"]
666pub type CH11_DBG_TCR = crate::Reg<ch11_dbg_tcr::CH11_DBG_TCR_SPEC>;
667#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"]
668pub mod ch11_dbg_tcr;
rp2040_pac/dma.rs

rp2040_pac/
dma.rs
