rp2040_pac/xip_ssi/
imr.rs

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1#[doc = "Register `IMR` reader"]
2pub type R = crate::R<IMR_SPEC>;
3#[doc = "Register `IMR` writer"]
4pub type W = crate::W<IMR_SPEC>;
5#[doc = "Field `TXEIM` reader - Transmit FIFO empty interrupt mask"]
6pub type TXEIM_R = crate::BitReader;
7#[doc = "Field `TXEIM` writer - Transmit FIFO empty interrupt mask"]
8pub type TXEIM_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXOIM` reader - Transmit FIFO overflow interrupt mask"]
10pub type TXOIM_R = crate::BitReader;
11#[doc = "Field `TXOIM` writer - Transmit FIFO overflow interrupt mask"]
12pub type TXOIM_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXUIM` reader - Receive FIFO underflow interrupt mask"]
14pub type RXUIM_R = crate::BitReader;
15#[doc = "Field `RXUIM` writer - Receive FIFO underflow interrupt mask"]
16pub type RXUIM_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RXOIM` reader - Receive FIFO overflow interrupt mask"]
18pub type RXOIM_R = crate::BitReader;
19#[doc = "Field `RXOIM` writer - Receive FIFO overflow interrupt mask"]
20pub type RXOIM_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RXFIM` reader - Receive FIFO full interrupt mask"]
22pub type RXFIM_R = crate::BitReader;
23#[doc = "Field `RXFIM` writer - Receive FIFO full interrupt mask"]
24pub type RXFIM_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `MSTIM` reader - Multi-master contention interrupt mask"]
26pub type MSTIM_R = crate::BitReader;
27#[doc = "Field `MSTIM` writer - Multi-master contention interrupt mask"]
28pub type MSTIM_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - Transmit FIFO empty interrupt mask"]
31    #[inline(always)]
32    pub fn txeim(&self) -> TXEIM_R {
33        TXEIM_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - Transmit FIFO overflow interrupt mask"]
36    #[inline(always)]
37    pub fn txoim(&self) -> TXOIM_R {
38        TXOIM_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - Receive FIFO underflow interrupt mask"]
41    #[inline(always)]
42    pub fn rxuim(&self) -> RXUIM_R {
43        RXUIM_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - Receive FIFO overflow interrupt mask"]
46    #[inline(always)]
47    pub fn rxoim(&self) -> RXOIM_R {
48        RXOIM_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - Receive FIFO full interrupt mask"]
51    #[inline(always)]
52    pub fn rxfim(&self) -> RXFIM_R {
53        RXFIM_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - Multi-master contention interrupt mask"]
56    #[inline(always)]
57    pub fn mstim(&self) -> MSTIM_R {
58        MSTIM_R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - Transmit FIFO empty interrupt mask"]
63    #[inline(always)]
64    #[must_use]
65    pub fn txeim(&mut self) -> TXEIM_W<IMR_SPEC> {
66        TXEIM_W::new(self, 0)
67    }
68    #[doc = "Bit 1 - Transmit FIFO overflow interrupt mask"]
69    #[inline(always)]
70    #[must_use]
71    pub fn txoim(&mut self) -> TXOIM_W<IMR_SPEC> {
72        TXOIM_W::new(self, 1)
73    }
74    #[doc = "Bit 2 - Receive FIFO underflow interrupt mask"]
75    #[inline(always)]
76    #[must_use]
77    pub fn rxuim(&mut self) -> RXUIM_W<IMR_SPEC> {
78        RXUIM_W::new(self, 2)
79    }
80    #[doc = "Bit 3 - Receive FIFO overflow interrupt mask"]
81    #[inline(always)]
82    #[must_use]
83    pub fn rxoim(&mut self) -> RXOIM_W<IMR_SPEC> {
84        RXOIM_W::new(self, 3)
85    }
86    #[doc = "Bit 4 - Receive FIFO full interrupt mask"]
87    #[inline(always)]
88    #[must_use]
89    pub fn rxfim(&mut self) -> RXFIM_W<IMR_SPEC> {
90        RXFIM_W::new(self, 4)
91    }
92    #[doc = "Bit 5 - Multi-master contention interrupt mask"]
93    #[inline(always)]
94    #[must_use]
95    pub fn mstim(&mut self) -> MSTIM_W<IMR_SPEC> {
96        MSTIM_W::new(self, 5)
97    }
98    #[doc = r" Writes raw bits to the register."]
99    #[doc = r""]
100    #[doc = r" # Safety"]
101    #[doc = r""]
102    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
103    #[inline(always)]
104    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
105        self.bits = bits;
106        self
107    }
108}
109#[doc = "Interrupt mask  
110
111You can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
112pub struct IMR_SPEC;
113impl crate::RegisterSpec for IMR_SPEC {
114    type Ux = u32;
115}
116#[doc = "`read()` method returns [`imr::R`](R) reader structure"]
117impl crate::Readable for IMR_SPEC {}
118#[doc = "`write(|w| ..)` method takes [`imr::W`](W) writer structure"]
119impl crate::Writable for IMR_SPEC {
120    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
121    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
122}
123#[doc = "`reset()` method sets IMR to value 0"]
124impl crate::Resettable for IMR_SPEC {
125    const RESET_VALUE: u32 = 0;
126}
rp2040_pac/xip_ssi/imr.rs

rp2040_pac/xip_ssi/
imr.rs
