cortex_m/peripheral/
fpu.rs

1//! Floating Point Unit
2//!
3//! *NOTE* Available only on targets with a Floating Point Unit (FPU) extension.
4
5use volatile_register::{RO, RW};
6
7/// Register block
8#[repr(C)]
9pub struct RegisterBlock {
10    reserved: u32,
11    /// Floating Point Context Control
12    pub fpccr: RW<u32>,
13    /// Floating Point Context Address
14    pub fpcar: RW<u32>,
15    /// Floating Point Default Status Control
16    pub fpdscr: RW<u32>,
17    /// Media and FP Feature
18    pub mvfr: [RO<u32>; 3],
19}