rp2040_pac/ppb/
mpu_rasr.rs

Help
1#[doc = "Register `MPU_RASR` reader"]
2pub type R = crate::R<MPU_RASR_SPEC>;
3#[doc = "Register `MPU_RASR` writer"]
4pub type W = crate::W<MPU_RASR_SPEC>;
5#[doc = "Field `ENABLE` reader - Enables the region."]
6pub type ENABLE_R = crate::BitReader;
7#[doc = "Field `ENABLE` writer - Enables the region."]
8pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SIZE` reader - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes"]
10pub type SIZE_R = crate::FieldReader;
11#[doc = "Field `SIZE` writer - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes"]
12pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `SRD` reader - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled."]
14pub type SRD_R = crate::FieldReader;
15#[doc = "Field `SRD` writer - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled."]
16pub type SRD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `ATTRS` reader - The MPU Region Attribute field. Use to define the region attribute control.  
18 28 = XN: Instruction access disable bit:  
19 0 = Instruction fetches enabled.  
20 1 = Instruction fetches disabled.  
21 26:24 = AP: Access permission field  
22 18 = S: Shareable bit  
23 17 = C: Cacheable bit  
24 16 = B: Bufferable bit"]
25pub type ATTRS_R = crate::FieldReader<u16>;
26#[doc = "Field `ATTRS` writer - The MPU Region Attribute field. Use to define the region attribute control.  
27 28 = XN: Instruction access disable bit:  
28 0 = Instruction fetches enabled.  
29 1 = Instruction fetches disabled.  
30 26:24 = AP: Access permission field  
31 18 = S: Shareable bit  
32 17 = C: Cacheable bit  
33 16 = B: Bufferable bit"]
34pub type ATTRS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
35impl R {
36    #[doc = "Bit 0 - Enables the region."]
37    #[inline(always)]
38    pub fn enable(&self) -> ENABLE_R {
39        ENABLE_R::new((self.bits & 1) != 0)
40    }
41    #[doc = "Bits 1:5 - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes"]
42    #[inline(always)]
43    pub fn size(&self) -> SIZE_R {
44        SIZE_R::new(((self.bits >> 1) & 0x1f) as u8)
45    }
46    #[doc = "Bits 8:15 - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled."]
47    #[inline(always)]
48    pub fn srd(&self) -> SRD_R {
49        SRD_R::new(((self.bits >> 8) & 0xff) as u8)
50    }
51    #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control.  
52 28 = XN: Instruction access disable bit:  
53 0 = Instruction fetches enabled.  
54 1 = Instruction fetches disabled.  
55 26:24 = AP: Access permission field  
56 18 = S: Shareable bit  
57 17 = C: Cacheable bit  
58 16 = B: Bufferable bit"]
59    #[inline(always)]
60    pub fn attrs(&self) -> ATTRS_R {
61        ATTRS_R::new(((self.bits >> 16) & 0xffff) as u16)
62    }
63}
64impl W {
65    #[doc = "Bit 0 - Enables the region."]
66    #[inline(always)]
67    #[must_use]
68    pub fn enable(&mut self) -> ENABLE_W<MPU_RASR_SPEC> {
69        ENABLE_W::new(self, 0)
70    }
71    #[doc = "Bits 1:5 - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes"]
72    #[inline(always)]
73    #[must_use]
74    pub fn size(&mut self) -> SIZE_W<MPU_RASR_SPEC> {
75        SIZE_W::new(self, 1)
76    }
77    #[doc = "Bits 8:15 - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled."]
78    #[inline(always)]
79    #[must_use]
80    pub fn srd(&mut self) -> SRD_W<MPU_RASR_SPEC> {
81        SRD_W::new(self, 8)
82    }
83    #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control.  
84 28 = XN: Instruction access disable bit:  
85 0 = Instruction fetches enabled.  
86 1 = Instruction fetches disabled.  
87 26:24 = AP: Access permission field  
88 18 = S: Shareable bit  
89 17 = C: Cacheable bit  
90 16 = B: Bufferable bit"]
91    #[inline(always)]
92    #[must_use]
93    pub fn attrs(&mut self) -> ATTRS_W<MPU_RASR_SPEC> {
94        ATTRS_W::new(self, 16)
95    }
96    #[doc = r" Writes raw bits to the register."]
97    #[doc = r""]
98    #[doc = r" # Safety"]
99    #[doc = r""]
100    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
103        self.bits = bits;
104        self
105    }
106}
107#[doc = "Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.  
108
109You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rasr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rasr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
110pub struct MPU_RASR_SPEC;
111impl crate::RegisterSpec for MPU_RASR_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [`mpu_rasr::R`](R) reader structure"]
115impl crate::Readable for MPU_RASR_SPEC {}
116#[doc = "`write(|w| ..)` method takes [`mpu_rasr::W`](W) writer structure"]
117impl crate::Writable for MPU_RASR_SPEC {
118    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
119    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
120}
121#[doc = "`reset()` method sets MPU_RASR to value 0"]
122impl crate::Resettable for MPU_RASR_SPEC {
123    const RESET_VALUE: u32 = 0;
124}
rp2040_pac/ppb/mpu_rasr.rs

rp2040_pac/ppb/
mpu_rasr.rs
