rp2040_pac/dma/
intr.rs

1#[doc = "Register `INTR` reader"]
2pub type R = crate::R<INTR_SPEC>;
3#[doc = "Register `INTR` writer"]
4pub type W = crate::W<INTR_SPEC>;
5#[doc = "Field `INTR` reader - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.  
6
7 Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.  
8
9 This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.  
10
11 It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."]
12pub type INTR_R = crate::FieldReader<u16>;
13#[doc = "Field `INTR` writer - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.  
14
15 Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.  
16
17 This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.  
18
19 It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."]
20pub type INTR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
21impl R {
22    #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.  
23
24 Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.  
25
26 This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.  
27
28 It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."]
29    #[inline(always)]
30    pub fn intr(&self) -> INTR_R {
31        INTR_R::new((self.bits & 0xffff) as u16)
32    }
33}
34impl W {
35    #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.  
36
37 Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.  
38
39 This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.  
40
41 It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."]
42    #[inline(always)]
43    #[must_use]
44    pub fn intr(&mut self) -> INTR_W<INTR_SPEC> {
45        INTR_W::new(self, 0)
46    }
47    #[doc = r" Writes raw bits to the register."]
48    #[doc = r""]
49    #[doc = r" # Safety"]
50    #[doc = r""]
51    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
52    #[inline(always)]
53    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
54        self.bits = bits;
55        self
56    }
57}
58#[doc = "Interrupt Status (raw)  
59
60You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct INTR_SPEC;
62impl crate::RegisterSpec for INTR_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`intr::R`](R) reader structure"]
66impl crate::Readable for INTR_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"]
68impl crate::Writable for INTR_SPEC {
69    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
70    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff;
71}
72#[doc = "`reset()` method sets INTR to value 0"]
73impl crate::Resettable for INTR_SPEC {
74    const RESET_VALUE: u32 = 0;
75}
rp2040_pac/dma/intr.rs

rp2040_pac/dma/
intr.rs
