rp2040_pac/rosc/
freqb.rs

Help
1#[doc = "Register `FREQB` reader"]
2pub type R = crate::R<FREQB_SPEC>;
3#[doc = "Register `FREQB` writer"]
4pub type W = crate::W<FREQB_SPEC>;
5#[doc = "Field `DS4` reader - Stage 4 drive strength"]
6pub type DS4_R = crate::FieldReader;
7#[doc = "Field `DS4` writer - Stage 4 drive strength"]
8pub type DS4_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `DS5` reader - Stage 5 drive strength"]
10pub type DS5_R = crate::FieldReader;
11#[doc = "Field `DS5` writer - Stage 5 drive strength"]
12pub type DS5_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `DS6` reader - Stage 6 drive strength"]
14pub type DS6_R = crate::FieldReader;
15#[doc = "Field `DS6` writer - Stage 6 drive strength"]
16pub type DS6_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `DS7` reader - Stage 7 drive strength"]
18pub type DS7_R = crate::FieldReader;
19#[doc = "Field `DS7` writer - Stage 7 drive strength"]
20pub type DS7_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings  
22 Any other value in this field will set all drive strengths to 0"]
23pub type PASSWD_R = crate::FieldReader<PASSWD_A>;
24#[doc = "Set to 0x9696 to apply the settings  
25 Any other value in this field will set all drive strengths to 0  
26
27Value on reset: 0"]
28#[derive(Clone, Copy, Debug, PartialEq, Eq)]
29#[repr(u16)]
30pub enum PASSWD_A {
31    #[doc = "38550: `1001011010010110`"]
32    PASS = 38550,
33}
34impl From<PASSWD_A> for u16 {
35    #[inline(always)]
36    fn from(variant: PASSWD_A) -> Self {
37        variant as _
38    }
39}
40impl crate::FieldSpec for PASSWD_A {
41    type Ux = u16;
42}
43impl PASSWD_R {
44    #[doc = "Get enumerated values variant"]
45    #[inline(always)]
46    pub const fn variant(&self) -> Option<PASSWD_A> {
47        match self.bits {
48            38550 => Some(PASSWD_A::PASS),
49            _ => None,
50        }
51    }
52    #[doc = "`1001011010010110`"]
53    #[inline(always)]
54    pub fn is_pass(&self) -> bool {
55        *self == PASSWD_A::PASS
56    }
57}
58#[doc = "Field `PASSWD` writer - Set to 0x9696 to apply the settings  
59 Any other value in this field will set all drive strengths to 0"]
60pub type PASSWD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, PASSWD_A>;
61impl<'a, REG> PASSWD_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64    REG::Ux: From<u16>,
65{
66    #[doc = "`1001011010010110`"]
67    #[inline(always)]
68    pub fn pass(self) -> &'a mut crate::W<REG> {
69        self.variant(PASSWD_A::PASS)
70    }
71}
72impl R {
73    #[doc = "Bits 0:2 - Stage 4 drive strength"]
74    #[inline(always)]
75    pub fn ds4(&self) -> DS4_R {
76        DS4_R::new((self.bits & 7) as u8)
77    }
78    #[doc = "Bits 4:6 - Stage 5 drive strength"]
79    #[inline(always)]
80    pub fn ds5(&self) -> DS5_R {
81        DS5_R::new(((self.bits >> 4) & 7) as u8)
82    }
83    #[doc = "Bits 8:10 - Stage 6 drive strength"]
84    #[inline(always)]
85    pub fn ds6(&self) -> DS6_R {
86        DS6_R::new(((self.bits >> 8) & 7) as u8)
87    }
88    #[doc = "Bits 12:14 - Stage 7 drive strength"]
89    #[inline(always)]
90    pub fn ds7(&self) -> DS7_R {
91        DS7_R::new(((self.bits >> 12) & 7) as u8)
92    }
93    #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings  
94 Any other value in this field will set all drive strengths to 0"]
95    #[inline(always)]
96    pub fn passwd(&self) -> PASSWD_R {
97        PASSWD_R::new(((self.bits >> 16) & 0xffff) as u16)
98    }
99}
100impl W {
101    #[doc = "Bits 0:2 - Stage 4 drive strength"]
102    #[inline(always)]
103    #[must_use]
104    pub fn ds4(&mut self) -> DS4_W<FREQB_SPEC> {
105        DS4_W::new(self, 0)
106    }
107    #[doc = "Bits 4:6 - Stage 5 drive strength"]
108    #[inline(always)]
109    #[must_use]
110    pub fn ds5(&mut self) -> DS5_W<FREQB_SPEC> {
111        DS5_W::new(self, 4)
112    }
113    #[doc = "Bits 8:10 - Stage 6 drive strength"]
114    #[inline(always)]
115    #[must_use]
116    pub fn ds6(&mut self) -> DS6_W<FREQB_SPEC> {
117        DS6_W::new(self, 8)
118    }
119    #[doc = "Bits 12:14 - Stage 7 drive strength"]
120    #[inline(always)]
121    #[must_use]
122    pub fn ds7(&mut self) -> DS7_W<FREQB_SPEC> {
123        DS7_W::new(self, 12)
124    }
125    #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings  
126 Any other value in this field will set all drive strengths to 0"]
127    #[inline(always)]
128    #[must_use]
129    pub fn passwd(&mut self) -> PASSWD_W<FREQB_SPEC> {
130        PASSWD_W::new(self, 16)
131    }
132    #[doc = r" Writes raw bits to the register."]
133    #[doc = r""]
134    #[doc = r" # Safety"]
135    #[doc = r""]
136    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
137    #[inline(always)]
138    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
139        self.bits = bits;
140        self
141    }
142}
143#[doc = "For a detailed description see freqa register  
144
145You can [`read`](crate::generic::Reg::read) this register and get [`freqb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
146pub struct FREQB_SPEC;
147impl crate::RegisterSpec for FREQB_SPEC {
148    type Ux = u32;
149}
150#[doc = "`read()` method returns [`freqb::R`](R) reader structure"]
151impl crate::Readable for FREQB_SPEC {}
152#[doc = "`write(|w| ..)` method takes [`freqb::W`](W) writer structure"]
153impl crate::Writable for FREQB_SPEC {
154    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
155    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
156}
157#[doc = "`reset()` method sets FREQB to value 0"]
158impl crate::Resettable for FREQB_SPEC {
159    const RESET_VALUE: u32 = 0;
160}
rp2040_pac/rosc/freqb.rs

rp2040_pac/rosc/
freqb.rs
