rp2040_pac/adc/
fcs.rs

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1#[doc = "Register `FCS` reader"]
2pub type R = crate::R<FCS_SPEC>;
3#[doc = "Register `FCS` writer"]
4pub type W = crate::W<FCS_SPEC>;
5#[doc = "Field `EN` reader - If 1: write result to the FIFO after each conversion."]
6pub type EN_R = crate::BitReader;
7#[doc = "Field `EN` writer - If 1: write result to the FIFO after each conversion."]
8pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SHIFT` reader - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."]
10pub type SHIFT_R = crate::BitReader;
11#[doc = "Field `SHIFT` writer - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."]
12pub type SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ERR` reader - If 1: conversion error bit appears in the FIFO alongside the result"]
14pub type ERR_R = crate::BitReader;
15#[doc = "Field `ERR` writer - If 1: conversion error bit appears in the FIFO alongside the result"]
16pub type ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DREQ_EN` reader - If 1: assert DMA requests when FIFO contains data"]
18pub type DREQ_EN_R = crate::BitReader;
19#[doc = "Field `DREQ_EN` writer - If 1: assert DMA requests when FIFO contains data"]
20pub type DREQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `EMPTY` reader - "]
22pub type EMPTY_R = crate::BitReader;
23#[doc = "Field `FULL` reader - "]
24pub type FULL_R = crate::BitReader;
25#[doc = "Field `UNDER` reader - 1 if the FIFO has been underflowed. Write 1 to clear."]
26pub type UNDER_R = crate::BitReader;
27#[doc = "Field `UNDER` writer - 1 if the FIFO has been underflowed. Write 1 to clear."]
28pub type UNDER_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `OVER` reader - 1 if the FIFO has been overflowed. Write 1 to clear."]
30pub type OVER_R = crate::BitReader;
31#[doc = "Field `OVER` writer - 1 if the FIFO has been overflowed. Write 1 to clear."]
32pub type OVER_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `LEVEL` reader - The number of conversion results currently waiting in the FIFO"]
34pub type LEVEL_R = crate::FieldReader;
35#[doc = "Field `THRESH` reader - DREQ/IRQ asserted when level >= threshold"]
36pub type THRESH_R = crate::FieldReader;
37#[doc = "Field `THRESH` writer - DREQ/IRQ asserted when level >= threshold"]
38pub type THRESH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
39impl R {
40    #[doc = "Bit 0 - If 1: write result to the FIFO after each conversion."]
41    #[inline(always)]
42    pub fn en(&self) -> EN_R {
43        EN_R::new((self.bits & 1) != 0)
44    }
45    #[doc = "Bit 1 - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."]
46    #[inline(always)]
47    pub fn shift(&self) -> SHIFT_R {
48        SHIFT_R::new(((self.bits >> 1) & 1) != 0)
49    }
50    #[doc = "Bit 2 - If 1: conversion error bit appears in the FIFO alongside the result"]
51    #[inline(always)]
52    pub fn err(&self) -> ERR_R {
53        ERR_R::new(((self.bits >> 2) & 1) != 0)
54    }
55    #[doc = "Bit 3 - If 1: assert DMA requests when FIFO contains data"]
56    #[inline(always)]
57    pub fn dreq_en(&self) -> DREQ_EN_R {
58        DREQ_EN_R::new(((self.bits >> 3) & 1) != 0)
59    }
60    #[doc = "Bit 8"]
61    #[inline(always)]
62    pub fn empty(&self) -> EMPTY_R {
63        EMPTY_R::new(((self.bits >> 8) & 1) != 0)
64    }
65    #[doc = "Bit 9"]
66    #[inline(always)]
67    pub fn full(&self) -> FULL_R {
68        FULL_R::new(((self.bits >> 9) & 1) != 0)
69    }
70    #[doc = "Bit 10 - 1 if the FIFO has been underflowed. Write 1 to clear."]
71    #[inline(always)]
72    pub fn under(&self) -> UNDER_R {
73        UNDER_R::new(((self.bits >> 10) & 1) != 0)
74    }
75    #[doc = "Bit 11 - 1 if the FIFO has been overflowed. Write 1 to clear."]
76    #[inline(always)]
77    pub fn over(&self) -> OVER_R {
78        OVER_R::new(((self.bits >> 11) & 1) != 0)
79    }
80    #[doc = "Bits 16:19 - The number of conversion results currently waiting in the FIFO"]
81    #[inline(always)]
82    pub fn level(&self) -> LEVEL_R {
83        LEVEL_R::new(((self.bits >> 16) & 0x0f) as u8)
84    }
85    #[doc = "Bits 24:27 - DREQ/IRQ asserted when level >= threshold"]
86    #[inline(always)]
87    pub fn thresh(&self) -> THRESH_R {
88        THRESH_R::new(((self.bits >> 24) & 0x0f) as u8)
89    }
90}
91impl W {
92    #[doc = "Bit 0 - If 1: write result to the FIFO after each conversion."]
93    #[inline(always)]
94    #[must_use]
95    pub fn en(&mut self) -> EN_W<FCS_SPEC> {
96        EN_W::new(self, 0)
97    }
98    #[doc = "Bit 1 - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."]
99    #[inline(always)]
100    #[must_use]
101    pub fn shift(&mut self) -> SHIFT_W<FCS_SPEC> {
102        SHIFT_W::new(self, 1)
103    }
104    #[doc = "Bit 2 - If 1: conversion error bit appears in the FIFO alongside the result"]
105    #[inline(always)]
106    #[must_use]
107    pub fn err(&mut self) -> ERR_W<FCS_SPEC> {
108        ERR_W::new(self, 2)
109    }
110    #[doc = "Bit 3 - If 1: assert DMA requests when FIFO contains data"]
111    #[inline(always)]
112    #[must_use]
113    pub fn dreq_en(&mut self) -> DREQ_EN_W<FCS_SPEC> {
114        DREQ_EN_W::new(self, 3)
115    }
116    #[doc = "Bit 10 - 1 if the FIFO has been underflowed. Write 1 to clear."]
117    #[inline(always)]
118    #[must_use]
119    pub fn under(&mut self) -> UNDER_W<FCS_SPEC> {
120        UNDER_W::new(self, 10)
121    }
122    #[doc = "Bit 11 - 1 if the FIFO has been overflowed. Write 1 to clear."]
123    #[inline(always)]
124    #[must_use]
125    pub fn over(&mut self) -> OVER_W<FCS_SPEC> {
126        OVER_W::new(self, 11)
127    }
128    #[doc = "Bits 24:27 - DREQ/IRQ asserted when level >= threshold"]
129    #[inline(always)]
130    #[must_use]
131    pub fn thresh(&mut self) -> THRESH_W<FCS_SPEC> {
132        THRESH_W::new(self, 24)
133    }
134    #[doc = r" Writes raw bits to the register."]
135    #[doc = r""]
136    #[doc = r" # Safety"]
137    #[doc = r""]
138    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
139    #[inline(always)]
140    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
141        self.bits = bits;
142        self
143    }
144}
145#[doc = "FIFO control and status  
146
147You can [`read`](crate::generic::Reg::read) this register and get [`fcs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
148pub struct FCS_SPEC;
149impl crate::RegisterSpec for FCS_SPEC {
150    type Ux = u32;
151}
152#[doc = "`read()` method returns [`fcs::R`](R) reader structure"]
153impl crate::Readable for FCS_SPEC {}
154#[doc = "`write(|w| ..)` method takes [`fcs::W`](W) writer structure"]
155impl crate::Writable for FCS_SPEC {
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0c00;
158}
159#[doc = "`reset()` method sets FCS to value 0"]
160impl crate::Resettable for FCS_SPEC {
161    const RESET_VALUE: u32 = 0;
162}
rp2040_pac/adc/fcs.rs

rp2040_pac/adc/
fcs.rs
