rp2040_pac/i2c0/
ic_dma_rdlr.rs

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1#[doc = "Register `IC_DMA_RDLR` reader"]
2pub type R = crate::R<IC_DMA_RDLR_SPEC>;
3#[doc = "Register `IC_DMA_RDLR` writer"]
4pub type W = crate::W<IC_DMA_RDLR_SPEC>;
5#[doc = "Field `DMARDL` reader - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.  
6
7 Reset value: 0x0"]
8pub type DMARDL_R = crate::FieldReader;
9#[doc = "Field `DMARDL` writer - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.  
10
11 Reset value: 0x0"]
12pub type DMARDL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.  
15
16 Reset value: 0x0"]
17    #[inline(always)]
18    pub fn dmardl(&self) -> DMARDL_R {
19        DMARDL_R::new((self.bits & 0x0f) as u8)
20    }
21}
22impl W {
23    #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.  
24
25 Reset value: 0x0"]
26    #[inline(always)]
27    #[must_use]
28    pub fn dmardl(&mut self) -> DMARDL_W<IC_DMA_RDLR_SPEC> {
29        DMARDL_W::new(self, 0)
30    }
31    #[doc = r" Writes raw bits to the register."]
32    #[doc = r""]
33    #[doc = r" # Safety"]
34    #[doc = r""]
35    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
36    #[inline(always)]
37    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
38        self.bits = bits;
39        self
40    }
41}
42#[doc = "I2C Receive Data Level Register  
43
44You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_rdlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
45pub struct IC_DMA_RDLR_SPEC;
46impl crate::RegisterSpec for IC_DMA_RDLR_SPEC {
47    type Ux = u32;
48}
49#[doc = "`read()` method returns [`ic_dma_rdlr::R`](R) reader structure"]
50impl crate::Readable for IC_DMA_RDLR_SPEC {}
51#[doc = "`write(|w| ..)` method takes [`ic_dma_rdlr::W`](W) writer structure"]
52impl crate::Writable for IC_DMA_RDLR_SPEC {
53    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
54    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
55}
56#[doc = "`reset()` method sets IC_DMA_RDLR to value 0"]
57impl crate::Resettable for IC_DMA_RDLR_SPEC {
58    const RESET_VALUE: u32 = 0;
59}
rp2040_pac/i2c0/ic_dma_rdlr.rs

rp2040_pac/i2c0/
ic_dma_rdlr.rs
