rp2040_pac/pll_sys/
prim.rs

Help
1#[doc = "Register `PRIM` reader"]
2pub type R = crate::R<PRIM_SPEC>;
3#[doc = "Register `PRIM` writer"]
4pub type W = crate::W<PRIM_SPEC>;
5#[doc = "Field `POSTDIV2` reader - divide by 1-7"]
6pub type POSTDIV2_R = crate::FieldReader;
7#[doc = "Field `POSTDIV2` writer - divide by 1-7"]
8pub type POSTDIV2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `POSTDIV1` reader - divide by 1-7"]
10pub type POSTDIV1_R = crate::FieldReader;
11#[doc = "Field `POSTDIV1` writer - divide by 1-7"]
12pub type POSTDIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13impl R {
14    #[doc = "Bits 12:14 - divide by 1-7"]
15    #[inline(always)]
16    pub fn postdiv2(&self) -> POSTDIV2_R {
17        POSTDIV2_R::new(((self.bits >> 12) & 7) as u8)
18    }
19    #[doc = "Bits 16:18 - divide by 1-7"]
20    #[inline(always)]
21    pub fn postdiv1(&self) -> POSTDIV1_R {
22        POSTDIV1_R::new(((self.bits >> 16) & 7) as u8)
23    }
24}
25impl W {
26    #[doc = "Bits 12:14 - divide by 1-7"]
27    #[inline(always)]
28    #[must_use]
29    pub fn postdiv2(&mut self) -> POSTDIV2_W<PRIM_SPEC> {
30        POSTDIV2_W::new(self, 12)
31    }
32    #[doc = "Bits 16:18 - divide by 1-7"]
33    #[inline(always)]
34    #[must_use]
35    pub fn postdiv1(&mut self) -> POSTDIV1_W<PRIM_SPEC> {
36        POSTDIV1_W::new(self, 16)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "Controls the PLL post dividers for the primary output  
50 (note: this PLL does not have a secondary output)  
51 the primary output is driven from VCO divided by postdiv1*postdiv2  
52
53You can [`read`](crate::generic::Reg::read) this register and get [`prim::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct PRIM_SPEC;
55impl crate::RegisterSpec for PRIM_SPEC {
56    type Ux = u32;
57}
58#[doc = "`read()` method returns [`prim::R`](R) reader structure"]
59impl crate::Readable for PRIM_SPEC {}
60#[doc = "`write(|w| ..)` method takes [`prim::W`](W) writer structure"]
61impl crate::Writable for PRIM_SPEC {
62    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
64}
65#[doc = "`reset()` method sets PRIM to value 0x0007_7000"]
66impl crate::Resettable for PRIM_SPEC {
67    const RESET_VALUE: u32 = 0x0007_7000;
68}
rp2040_pac/pll_sys/prim.rs

rp2040_pac/pll_sys/
prim.rs
