rp2040_pac/
xip_ctrl.rs

Help
1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    ctrl: CTRL,
5    flush: FLUSH,
6    stat: STAT,
7    ctr_hit: CTR_HIT,
8    ctr_acc: CTR_ACC,
9    stream_addr: STREAM_ADDR,
10    stream_ctr: STREAM_CTR,
11    stream_fifo: STREAM_FIFO,
12}
13impl RegisterBlock {
14    #[doc = "0x00 - Cache control"]
15    #[inline(always)]
16    pub const fn ctrl(&self) -> &CTRL {
17        &self.ctrl
18    }
19    #[doc = "0x04 - Cache Flush control"]
20    #[inline(always)]
21    pub const fn flush(&self) -> &FLUSH {
22        &self.flush
23    }
24    #[doc = "0x08 - Cache Status"]
25    #[inline(always)]
26    pub const fn stat(&self) -> &STAT {
27        &self.stat
28    }
29    #[doc = "0x0c - Cache Hit counter  
30 A 32 bit saturating counter that increments upon each cache hit,  
31 i.e. when an XIP access is serviced directly from cached data.  
32 Write any value to clear."]
33    #[inline(always)]
34    pub const fn ctr_hit(&self) -> &CTR_HIT {
35        &self.ctr_hit
36    }
37    #[doc = "0x10 - Cache Access counter  
38 A 32 bit saturating counter that increments upon each XIP access,  
39 whether the cache is hit or not. This includes noncacheable accesses.  
40 Write any value to clear."]
41    #[inline(always)]
42    pub const fn ctr_acc(&self) -> &CTR_ACC {
43        &self.ctr_acc
44    }
45    #[doc = "0x14 - FIFO stream address"]
46    #[inline(always)]
47    pub const fn stream_addr(&self) -> &STREAM_ADDR {
48        &self.stream_addr
49    }
50    #[doc = "0x18 - FIFO stream control"]
51    #[inline(always)]
52    pub const fn stream_ctr(&self) -> &STREAM_CTR {
53        &self.stream_ctr
54    }
55    #[doc = "0x1c - FIFO stream data  
56 Streamed data is buffered here, for retrieval by the system DMA.  
57 This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing  
58 the DMA to bus stalls caused by other XIP traffic."]
59    #[inline(always)]
60    pub const fn stream_fifo(&self) -> &STREAM_FIFO {
61        &self.stream_fifo
62    }
63}
64#[doc = "CTRL (rw) register accessor: Cache control  
65
66You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
67
68For information about available fields see [`mod@ctrl`]
69module"]
70pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
71#[doc = "Cache control"]
72pub mod ctrl;
73#[doc = "FLUSH (rw) register accessor: Cache Flush control  
74
75You can [`read`](crate::generic::Reg::read) this register and get [`flush::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flush::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
76
77For information about available fields see [`mod@flush`]
78module"]
79pub type FLUSH = crate::Reg<flush::FLUSH_SPEC>;
80#[doc = "Cache Flush control"]
81pub mod flush;
82#[doc = "STAT (r) register accessor: Cache Status  
83
84You can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
85
86For information about available fields see [`mod@stat`]
87module"]
88pub type STAT = crate::Reg<stat::STAT_SPEC>;
89#[doc = "Cache Status"]
90pub mod stat;
91#[doc = "CTR_HIT (rw) register accessor: Cache Hit counter  
92 A 32 bit saturating counter that increments upon each cache hit,  
93 i.e. when an XIP access is serviced directly from cached data.  
94 Write any value to clear.  
95
96You can [`read`](crate::generic::Reg::read) this register and get [`ctr_hit::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_hit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
97
98For information about available fields see [`mod@ctr_hit`]
99module"]
100pub type CTR_HIT = crate::Reg<ctr_hit::CTR_HIT_SPEC>;
101#[doc = "Cache Hit counter  
102 A 32 bit saturating counter that increments upon each cache hit,  
103 i.e. when an XIP access is serviced directly from cached data.  
104 Write any value to clear."]
105pub mod ctr_hit;
106#[doc = "CTR_ACC (rw) register accessor: Cache Access counter  
107 A 32 bit saturating counter that increments upon each XIP access,  
108 whether the cache is hit or not. This includes noncacheable accesses.  
109 Write any value to clear.  
110
111You can [`read`](crate::generic::Reg::read) this register and get [`ctr_acc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_acc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
112
113For information about available fields see [`mod@ctr_acc`]
114module"]
115pub type CTR_ACC = crate::Reg<ctr_acc::CTR_ACC_SPEC>;
116#[doc = "Cache Access counter  
117 A 32 bit saturating counter that increments upon each XIP access,  
118 whether the cache is hit or not. This includes noncacheable accesses.  
119 Write any value to clear."]
120pub mod ctr_acc;
121#[doc = "STREAM_ADDR (rw) register accessor: FIFO stream address  
122
123You can [`read`](crate::generic::Reg::read) this register and get [`stream_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
124
125For information about available fields see [`mod@stream_addr`]
126module"]
127pub type STREAM_ADDR = crate::Reg<stream_addr::STREAM_ADDR_SPEC>;
128#[doc = "FIFO stream address"]
129pub mod stream_addr;
130#[doc = "STREAM_CTR (rw) register accessor: FIFO stream control  
131
132You can [`read`](crate::generic::Reg::read) this register and get [`stream_ctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
133
134For information about available fields see [`mod@stream_ctr`]
135module"]
136pub type STREAM_CTR = crate::Reg<stream_ctr::STREAM_CTR_SPEC>;
137#[doc = "FIFO stream control"]
138pub mod stream_ctr;
139#[doc = "STREAM_FIFO (r) register accessor: FIFO stream data  
140 Streamed data is buffered here, for retrieval by the system DMA.  
141 This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing  
142 the DMA to bus stalls caused by other XIP traffic.  
143
144You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
145
146For information about available fields see [`mod@stream_fifo`]
147module"]
148pub type STREAM_FIFO = crate::Reg<stream_fifo::STREAM_FIFO_SPEC>;
149#[doc = "FIFO stream data  
150 Streamed data is buffered here, for retrieval by the system DMA.  
151 This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing  
152 the DMA to bus stalls caused by other XIP traffic."]
153pub mod stream_fifo;
rp2040_pac/xip_ctrl.rs

rp2040_pac/
xip_ctrl.rs
