rp2040_pac/psm/
frce_on.rs

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1#[doc = "Register `FRCE_ON` reader"]
2pub type R = crate::R<FRCE_ON_SPEC>;
3#[doc = "Register `FRCE_ON` writer"]
4pub type W = crate::W<FRCE_ON_SPEC>;
5#[doc = "Field `rosc` reader - "]
6pub type ROSC_R = crate::BitReader;
7#[doc = "Field `rosc` writer - "]
8pub type ROSC_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `xosc` reader - "]
10pub type XOSC_R = crate::BitReader;
11#[doc = "Field `xosc` writer - "]
12pub type XOSC_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `clocks` reader - "]
14pub type CLOCKS_R = crate::BitReader;
15#[doc = "Field `clocks` writer - "]
16pub type CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `resets` reader - "]
18pub type RESETS_R = crate::BitReader;
19#[doc = "Field `resets` writer - "]
20pub type RESETS_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `busfabric` reader - "]
22pub type BUSFABRIC_R = crate::BitReader;
23#[doc = "Field `busfabric` writer - "]
24pub type BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `rom` reader - "]
26pub type ROM_R = crate::BitReader;
27#[doc = "Field `rom` writer - "]
28pub type ROM_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `sram0` reader - "]
30pub type SRAM0_R = crate::BitReader;
31#[doc = "Field `sram0` writer - "]
32pub type SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `sram1` reader - "]
34pub type SRAM1_R = crate::BitReader;
35#[doc = "Field `sram1` writer - "]
36pub type SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `sram2` reader - "]
38pub type SRAM2_R = crate::BitReader;
39#[doc = "Field `sram2` writer - "]
40pub type SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `sram3` reader - "]
42pub type SRAM3_R = crate::BitReader;
43#[doc = "Field `sram3` writer - "]
44pub type SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `sram4` reader - "]
46pub type SRAM4_R = crate::BitReader;
47#[doc = "Field `sram4` writer - "]
48pub type SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `sram5` reader - "]
50pub type SRAM5_R = crate::BitReader;
51#[doc = "Field `sram5` writer - "]
52pub type SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `xip` reader - "]
54pub type XIP_R = crate::BitReader;
55#[doc = "Field `xip` writer - "]
56pub type XIP_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `vreg_and_chip_reset` reader - "]
58pub type VREG_AND_CHIP_RESET_R = crate::BitReader;
59#[doc = "Field `vreg_and_chip_reset` writer - "]
60pub type VREG_AND_CHIP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `sio` reader - "]
62pub type SIO_R = crate::BitReader;
63#[doc = "Field `sio` writer - "]
64pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `proc0` reader - "]
66pub type PROC0_R = crate::BitReader;
67#[doc = "Field `proc0` writer - "]
68pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `proc1` reader - "]
70pub type PROC1_R = crate::BitReader;
71#[doc = "Field `proc1` writer - "]
72pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>;
73impl R {
74    #[doc = "Bit 0"]
75    #[inline(always)]
76    pub fn rosc(&self) -> ROSC_R {
77        ROSC_R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1"]
80    #[inline(always)]
81    pub fn xosc(&self) -> XOSC_R {
82        XOSC_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 2"]
85    #[inline(always)]
86    pub fn clocks(&self) -> CLOCKS_R {
87        CLOCKS_R::new(((self.bits >> 2) & 1) != 0)
88    }
89    #[doc = "Bit 3"]
90    #[inline(always)]
91    pub fn resets(&self) -> RESETS_R {
92        RESETS_R::new(((self.bits >> 3) & 1) != 0)
93    }
94    #[doc = "Bit 4"]
95    #[inline(always)]
96    pub fn busfabric(&self) -> BUSFABRIC_R {
97        BUSFABRIC_R::new(((self.bits >> 4) & 1) != 0)
98    }
99    #[doc = "Bit 5"]
100    #[inline(always)]
101    pub fn rom(&self) -> ROM_R {
102        ROM_R::new(((self.bits >> 5) & 1) != 0)
103    }
104    #[doc = "Bit 6"]
105    #[inline(always)]
106    pub fn sram0(&self) -> SRAM0_R {
107        SRAM0_R::new(((self.bits >> 6) & 1) != 0)
108    }
109    #[doc = "Bit 7"]
110    #[inline(always)]
111    pub fn sram1(&self) -> SRAM1_R {
112        SRAM1_R::new(((self.bits >> 7) & 1) != 0)
113    }
114    #[doc = "Bit 8"]
115    #[inline(always)]
116    pub fn sram2(&self) -> SRAM2_R {
117        SRAM2_R::new(((self.bits >> 8) & 1) != 0)
118    }
119    #[doc = "Bit 9"]
120    #[inline(always)]
121    pub fn sram3(&self) -> SRAM3_R {
122        SRAM3_R::new(((self.bits >> 9) & 1) != 0)
123    }
124    #[doc = "Bit 10"]
125    #[inline(always)]
126    pub fn sram4(&self) -> SRAM4_R {
127        SRAM4_R::new(((self.bits >> 10) & 1) != 0)
128    }
129    #[doc = "Bit 11"]
130    #[inline(always)]
131    pub fn sram5(&self) -> SRAM5_R {
132        SRAM5_R::new(((self.bits >> 11) & 1) != 0)
133    }
134    #[doc = "Bit 12"]
135    #[inline(always)]
136    pub fn xip(&self) -> XIP_R {
137        XIP_R::new(((self.bits >> 12) & 1) != 0)
138    }
139    #[doc = "Bit 13"]
140    #[inline(always)]
141    pub fn vreg_and_chip_reset(&self) -> VREG_AND_CHIP_RESET_R {
142        VREG_AND_CHIP_RESET_R::new(((self.bits >> 13) & 1) != 0)
143    }
144    #[doc = "Bit 14"]
145    #[inline(always)]
146    pub fn sio(&self) -> SIO_R {
147        SIO_R::new(((self.bits >> 14) & 1) != 0)
148    }
149    #[doc = "Bit 15"]
150    #[inline(always)]
151    pub fn proc0(&self) -> PROC0_R {
152        PROC0_R::new(((self.bits >> 15) & 1) != 0)
153    }
154    #[doc = "Bit 16"]
155    #[inline(always)]
156    pub fn proc1(&self) -> PROC1_R {
157        PROC1_R::new(((self.bits >> 16) & 1) != 0)
158    }
159}
160impl W {
161    #[doc = "Bit 0"]
162    #[inline(always)]
163    #[must_use]
164    pub fn rosc(&mut self) -> ROSC_W<FRCE_ON_SPEC> {
165        ROSC_W::new(self, 0)
166    }
167    #[doc = "Bit 1"]
168    #[inline(always)]
169    #[must_use]
170    pub fn xosc(&mut self) -> XOSC_W<FRCE_ON_SPEC> {
171        XOSC_W::new(self, 1)
172    }
173    #[doc = "Bit 2"]
174    #[inline(always)]
175    #[must_use]
176    pub fn clocks(&mut self) -> CLOCKS_W<FRCE_ON_SPEC> {
177        CLOCKS_W::new(self, 2)
178    }
179    #[doc = "Bit 3"]
180    #[inline(always)]
181    #[must_use]
182    pub fn resets(&mut self) -> RESETS_W<FRCE_ON_SPEC> {
183        RESETS_W::new(self, 3)
184    }
185    #[doc = "Bit 4"]
186    #[inline(always)]
187    #[must_use]
188    pub fn busfabric(&mut self) -> BUSFABRIC_W<FRCE_ON_SPEC> {
189        BUSFABRIC_W::new(self, 4)
190    }
191    #[doc = "Bit 5"]
192    #[inline(always)]
193    #[must_use]
194    pub fn rom(&mut self) -> ROM_W<FRCE_ON_SPEC> {
195        ROM_W::new(self, 5)
196    }
197    #[doc = "Bit 6"]
198    #[inline(always)]
199    #[must_use]
200    pub fn sram0(&mut self) -> SRAM0_W<FRCE_ON_SPEC> {
201        SRAM0_W::new(self, 6)
202    }
203    #[doc = "Bit 7"]
204    #[inline(always)]
205    #[must_use]
206    pub fn sram1(&mut self) -> SRAM1_W<FRCE_ON_SPEC> {
207        SRAM1_W::new(self, 7)
208    }
209    #[doc = "Bit 8"]
210    #[inline(always)]
211    #[must_use]
212    pub fn sram2(&mut self) -> SRAM2_W<FRCE_ON_SPEC> {
213        SRAM2_W::new(self, 8)
214    }
215    #[doc = "Bit 9"]
216    #[inline(always)]
217    #[must_use]
218    pub fn sram3(&mut self) -> SRAM3_W<FRCE_ON_SPEC> {
219        SRAM3_W::new(self, 9)
220    }
221    #[doc = "Bit 10"]
222    #[inline(always)]
223    #[must_use]
224    pub fn sram4(&mut self) -> SRAM4_W<FRCE_ON_SPEC> {
225        SRAM4_W::new(self, 10)
226    }
227    #[doc = "Bit 11"]
228    #[inline(always)]
229    #[must_use]
230    pub fn sram5(&mut self) -> SRAM5_W<FRCE_ON_SPEC> {
231        SRAM5_W::new(self, 11)
232    }
233    #[doc = "Bit 12"]
234    #[inline(always)]
235    #[must_use]
236    pub fn xip(&mut self) -> XIP_W<FRCE_ON_SPEC> {
237        XIP_W::new(self, 12)
238    }
239    #[doc = "Bit 13"]
240    #[inline(always)]
241    #[must_use]
242    pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W<FRCE_ON_SPEC> {
243        VREG_AND_CHIP_RESET_W::new(self, 13)
244    }
245    #[doc = "Bit 14"]
246    #[inline(always)]
247    #[must_use]
248    pub fn sio(&mut self) -> SIO_W<FRCE_ON_SPEC> {
249        SIO_W::new(self, 14)
250    }
251    #[doc = "Bit 15"]
252    #[inline(always)]
253    #[must_use]
254    pub fn proc0(&mut self) -> PROC0_W<FRCE_ON_SPEC> {
255        PROC0_W::new(self, 15)
256    }
257    #[doc = "Bit 16"]
258    #[inline(always)]
259    #[must_use]
260    pub fn proc1(&mut self) -> PROC1_W<FRCE_ON_SPEC> {
261        PROC1_W::new(self, 16)
262    }
263    #[doc = r" Writes raw bits to the register."]
264    #[doc = r""]
265    #[doc = r" # Safety"]
266    #[doc = r""]
267    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
268    #[inline(always)]
269    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
270        self.bits = bits;
271        self
272    }
273}
274#[doc = "Force block out of reset (i.e. power it on)  
275
276You can [`read`](crate::generic::Reg::read) this register and get [`frce_on::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frce_on::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct FRCE_ON_SPEC;
278impl crate::RegisterSpec for FRCE_ON_SPEC {
279    type Ux = u32;
280}
281#[doc = "`read()` method returns [`frce_on::R`](R) reader structure"]
282impl crate::Readable for FRCE_ON_SPEC {}
283#[doc = "`write(|w| ..)` method takes [`frce_on::W`](W) writer structure"]
284impl crate::Writable for FRCE_ON_SPEC {
285    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
286    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
287}
288#[doc = "`reset()` method sets FRCE_ON to value 0"]
289impl crate::Resettable for FRCE_ON_SPEC {
290    const RESET_VALUE: u32 = 0;
291}
rp2040_pac/psm/frce_on.rs

rp2040_pac/psm/
frce_on.rs
