Module clocks

CLOCKS

Modules

clk_adc_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_adc_div

Clock divisor, can be changed on-the-fly

clk_adc_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

clk_gpout0_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_gpout0_div

Clock divisor, can be changed on-the-fly

clk_gpout0_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

clk_gpout1_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_gpout1_div

Clock divisor, can be changed on-the-fly

clk_gpout1_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

clk_gpout2_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_gpout2_div

Clock divisor, can be changed on-the-fly

clk_gpout2_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

clk_gpout3_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_gpout3_div

Clock divisor, can be changed on-the-fly

clk_gpout3_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

clk_peri_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_peri_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

clk_ref_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_ref_div

Clock divisor, can be changed on-the-fly

clk_ref_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

clk_rtc_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_rtc_div

Clock divisor, can be changed on-the-fly

clk_rtc_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

clk_sys_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_sys_div

Clock divisor, can be changed on-the-fly

clk_sys_resus_ctrl

clk_sys_resus_status

clk_sys_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

clk_usb_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

clk_usb_div

Clock divisor, can be changed on-the-fly

clk_usb_selected

Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

enabled0

indicates the state of the clock enable

enabled1

indicates the state of the clock enable

fc0_delay

Delays the start of frequency counting to allow the mux to settle
Delay is measured in multiples of the reference clock period

fc0_interval

The test interval is 0.98us * 2interval, but let’s call it 1us * 2interval
The default gives a test interval of 250us

fc0_max_khz

Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags

fc0_min_khz

Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags

fc0_ref_khz

Reference clock frequency in kHz

fc0_result

Result of frequency measurement, only valid when status_done=1

fc0_src

Clock sent to frequency counter, set to 0 when not required
Writing to this register initiates the frequency count

fc0_status

Frequency counter status

inte

Interrupt Enable

intf

Interrupt Force

intr

Raw Interrupts

ints

Interrupt status after masking & forcing

sleep_en0

enable clock in sleep mode

sleep_en1

enable clock in sleep mode

wake_en0

enable clock in wake mode

wake_en1

enable clock in wake mode

Structs

RegisterBlock

Register block

Type Aliases

CLK_ADC_CTRL

CLK_ADC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_ADC_DIV

CLK_ADC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

CLK_ADC_SELECTED

CLK_ADC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

CLK_GPOUT0_CTRL

CLK_GPOUT0_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_GPOUT0_DIV

CLK_GPOUT0_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

CLK_GPOUT0_SELECTED

CLK_GPOUT0_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

CLK_GPOUT1_CTRL

CLK_GPOUT1_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_GPOUT1_DIV

CLK_GPOUT1_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

CLK_GPOUT1_SELECTED

CLK_GPOUT1_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

CLK_GPOUT2_CTRL

CLK_GPOUT2_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_GPOUT2_DIV

CLK_GPOUT2_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

CLK_GPOUT2_SELECTED

CLK_GPOUT2_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

CLK_GPOUT3_CTRL

CLK_GPOUT3_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_GPOUT3_DIV

CLK_GPOUT3_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

CLK_GPOUT3_SELECTED

CLK_GPOUT3_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

CLK_PERI_CTRL

CLK_PERI_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_PERI_SELECTED

CLK_PERI_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

CLK_REF_CTRL

CLK_REF_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_REF_DIV

CLK_REF_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

CLK_REF_SELECTED

CLK_REF_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

CLK_RTC_CTRL

CLK_RTC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_RTC_DIV

CLK_RTC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

CLK_RTC_SELECTED

CLK_RTC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

CLK_SYS_CTRL

CLK_SYS_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_SYS_DIV

CLK_SYS_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

CLK_SYS_RESUS_CTRL

CLK_SYS_RESUS_CTRL (rw) register accessor:

CLK_SYS_RESUS_STATUS

CLK_SYS_RESUS_STATUS (r) register accessor:

CLK_SYS_SELECTED

CLK_SYS_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

CLK_USB_CTRL

CLK_USB_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)

CLK_USB_DIV

CLK_USB_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

CLK_USB_SELECTED

CLK_USB_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

ENABLED0

ENABLED0 (r) register accessor: indicates the state of the clock enable

ENABLED1

ENABLED1 (r) register accessor: indicates the state of the clock enable

FC0_DELAY

FC0_DELAY (rw) register accessor: Delays the start of frequency counting to allow the mux to settle
Delay is measured in multiples of the reference clock period

FC0_INTERVAL

FC0_INTERVAL (rw) register accessor: The test interval is 0.98us * 2interval, but let’s call it 1us * 2interval
The default gives a test interval of 250us

FC0_MAX_KHZ

FC0_MAX_KHZ (rw) register accessor: Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags

FC0_MIN_KHZ

FC0_MIN_KHZ (rw) register accessor: Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags

FC0_REF_KHZ

FC0_REF_KHZ (rw) register accessor: Reference clock frequency in kHz

FC0_RESULT

FC0_RESULT (r) register accessor: Result of frequency measurement, only valid when status_done=1

FC0_SRC

FC0_SRC (rw) register accessor: Clock sent to frequency counter, set to 0 when not required
Writing to this register initiates the frequency count

FC0_STATUS

FC0_STATUS (r) register accessor: Frequency counter status

INTE

INTE (rw) register accessor: Interrupt Enable

INTF

INTF (rw) register accessor: Interrupt Force

INTR

INTR (r) register accessor: Raw Interrupts

INTS

INTS (r) register accessor: Interrupt status after masking & forcing

SLEEP_EN0

SLEEP_EN0 (rw) register accessor: enable clock in sleep mode

SLEEP_EN1

SLEEP_EN1 (rw) register accessor: enable clock in sleep mode

WAKE_EN0

WAKE_EN0 (rw) register accessor: enable clock in wake mode

WAKE_EN1

WAKE_EN1 (rw) register accessor: enable clock in wake mode