Module xip_ctrl

QSPI flash execute-in-place block

Modules

ctr_acc

Cache Access counter
A 32 bit saturating counter that increments upon each XIP access,
whether the cache is hit or not. This includes noncacheable accesses.
Write any value to clear.

ctr_hit

Cache Hit counter
A 32 bit saturating counter that increments upon each cache hit,
i.e. when an XIP access is serviced directly from cached data.
Write any value to clear.

ctrl

Cache control

flush

Cache Flush control

stat

Cache Status

stream_addr

FIFO stream address

stream_ctr

FIFO stream control

stream_fifo

FIFO stream data
Streamed data is buffered here, for retrieval by the system DMA.
This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing
the DMA to bus stalls caused by other XIP traffic.

Structs

RegisterBlock

Register block

Type Aliases

CTRL

CTRL (rw) register accessor: Cache control

CTR_ACC

CTR_ACC (rw) register accessor: Cache Access counter
A 32 bit saturating counter that increments upon each XIP access,
whether the cache is hit or not. This includes noncacheable accesses.
Write any value to clear.

CTR_HIT

CTR_HIT (rw) register accessor: Cache Hit counter
A 32 bit saturating counter that increments upon each cache hit,
i.e. when an XIP access is serviced directly from cached data.
Write any value to clear.

FLUSH

FLUSH (rw) register accessor: Cache Flush control

STAT

STAT (r) register accessor: Cache Status

STREAM_ADDR

STREAM_ADDR (rw) register accessor: FIFO stream address

STREAM_CTR

STREAM_CTR (rw) register accessor: FIFO stream control

STREAM_FIFO

STREAM_FIFO (r) register accessor: FIFO stream data
Streamed data is buffered here, for retrieval by the system DMA.
This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing
the DMA to bus stalls caused by other XIP traffic.