Module rp2040_pac::sio

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Expand description

Single-cycle IO block
Provides core-local and inter-core hardware for the two processors, with single-cycle access.

Modules§

  • Processor core identifier
    Value is 0 when read from processor core 0, and 1 when read from processor core 1.
  • Control and status register for divider.
  • Divider result quotient
    The result of DIVIDEND / DIVISOR (division). Contents undefined while CSR_READY is low.
    For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
    This register can be written to directly, for context save/restore purposes. This halts any
    in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
    Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
    REMAINDER, QUOTIENT if CSR_DIRTY is used.
  • Divider result remainder
    The result of DIVIDEND % DIVISOR (modulo). Contents undefined while CSR_READY is low.
    For signed calculations, REMAINDER is negative only when DIVIDEND is negative.
    This register can be written to directly, for context save/restore purposes. This halts any
    in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
  • Divider signed dividend
    The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
  • Divider signed divisor
    The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
  • Divider unsigned dividend
    Write to the DIVIDEND operand of the divider, i.e. the p in p / q.
    Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
    UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
    unsigned calculation, and the S alias starts a signed calculation.
  • Divider unsigned divisor
    Write to the DIVISOR operand of the divider, i.e. the q in p / q.
    Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
    UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an
    unsigned calculation, and the S alias starts a signed calculation.
  • Read access to this core’s RX FIFO
  • Status register for inter-core FIFOs (mailboxes).
    There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
    Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
    Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
    The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
  • Write access to this core’s TX FIFO
  • Input value for QSPI pins
  • QSPI output enable
  • QSPI output enable clear
  • QSPI output enable set
  • QSPI output enable XOR
  • QSPI output value
  • QSPI output value clear
  • QSPI output value set
  • QSPI output value XOR
  • Input value for GPIO pins
  • GPIO output enable
  • GPIO output enable clear
  • GPIO output enable set
  • GPIO output enable XOR
  • GPIO output value
  • GPIO output value clear
  • GPIO output value set
  • GPIO output value XOR
  • Read/write access to accumulator 0
  • Values written here are atomically added to ACCUM0
    Reading yields lane 0’s raw shift and mask value (BASE0 not added).
  • Read/write access to accumulator 1
  • Values written here are atomically added to ACCUM1
    Reading yields lane 1’s raw shift and mask value (BASE1 not added).
  • Read/write access to BASE0 register.
  • Read/write access to BASE1 register.
  • Read/write access to BASE2 register.
  • On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
    Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
  • Control register for lane 0
  • Control register for lane 1
  • Read FULL result, without altering any internal state (PEEK).
  • Read LANE0 result, without altering any internal state (PEEK).
  • Read LANE1 result, without altering any internal state (PEEK).
  • Read FULL result, and simultaneously write lane results to both accumulators (POP).
  • Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
  • Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
  • Read/write access to accumulator 0
  • Values written here are atomically added to ACCUM0
    Reading yields lane 0’s raw shift and mask value (BASE0 not added).
  • Read/write access to accumulator 1
  • Values written here are atomically added to ACCUM1
    Reading yields lane 1’s raw shift and mask value (BASE1 not added).
  • Read/write access to BASE0 register.
  • Read/write access to BASE1 register.
  • Read/write access to BASE2 register.
  • On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
    Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
  • Control register for lane 0
  • Control register for lane 1
  • Read FULL result, without altering any internal state (PEEK).
  • Read LANE0 result, without altering any internal state (PEEK).
  • Read LANE1 result, without altering any internal state (PEEK).
  • Read FULL result, and simultaneously write lane results to both accumulators (POP).
  • Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
  • Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
  • Reading from a spinlock address will:
  • Spinlock state
    A bitmap containing the state of all 32 spinlocks (1=locked).
    Mainly intended for debugging.

Structs§

Type Aliases§

  • CPUID (r) register accessor: Processor core identifier
    Value is 0 when read from processor core 0, and 1 when read from processor core 1.
  • DIV_CSR (r) register accessor: Control and status register for divider.
  • DIV_QUOTIENT (rw) register accessor: Divider result quotient
    The result of DIVIDEND / DIVISOR (division). Contents undefined while CSR_READY is low.
    For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
    This register can be written to directly, for context save/restore purposes. This halts any
    in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
    Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
    REMAINDER, QUOTIENT if CSR_DIRTY is used.
  • DIV_REMAINDER (rw) register accessor: Divider result remainder
    The result of DIVIDEND % DIVISOR (modulo). Contents undefined while CSR_READY is low.
    For signed calculations, REMAINDER is negative only when DIVIDEND is negative.
    This register can be written to directly, for context save/restore purposes. This halts any
    in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
  • DIV_SDIVIDEND (rw) register accessor: Divider signed dividend
    The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
  • DIV_SDIVISOR (rw) register accessor: Divider signed divisor
    The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
  • DIV_UDIVIDEND (rw) register accessor: Divider unsigned dividend
    Write to the DIVIDEND operand of the divider, i.e. the p in p / q.
    Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
    UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
    unsigned calculation, and the S alias starts a signed calculation.
  • DIV_UDIVISOR (rw) register accessor: Divider unsigned divisor
    Write to the DIVISOR operand of the divider, i.e. the q in p / q.
    Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
    UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an
    unsigned calculation, and the S alias starts a signed calculation.
  • FIFO_RD (r) register accessor: Read access to this core’s RX FIFO
  • FIFO_ST (rw) register accessor: Status register for inter-core FIFOs (mailboxes).
    There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
    Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
    Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
    The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
  • FIFO_WR (w) register accessor: Write access to this core’s TX FIFO
  • GPIO_HI_IN (r) register accessor: Input value for QSPI pins
  • GPIO_HI_OE (rw) register accessor: QSPI output enable
  • GPIO_HI_OE_CLR (w) register accessor: QSPI output enable clear
  • GPIO_HI_OE_SET (w) register accessor: QSPI output enable set
  • GPIO_HI_OE_XOR (w) register accessor: QSPI output enable XOR
  • GPIO_HI_OUT (rw) register accessor: QSPI output value
  • GPIO_HI_OUT_CLR (w) register accessor: QSPI output value clear
  • GPIO_HI_OUT_SET (w) register accessor: QSPI output value set
  • GPIO_HI_OUT_XOR (w) register accessor: QSPI output value XOR
  • GPIO_IN (r) register accessor: Input value for GPIO pins
  • GPIO_OE (rw) register accessor: GPIO output enable
  • GPIO_OE_CLR (w) register accessor: GPIO output enable clear
  • GPIO_OE_SET (w) register accessor: GPIO output enable set
  • GPIO_OE_XOR (w) register accessor: GPIO output enable XOR
  • GPIO_OUT (rw) register accessor: GPIO output value
  • GPIO_OUT_CLR (w) register accessor: GPIO output value clear
  • GPIO_OUT_SET (w) register accessor: GPIO output value set
  • GPIO_OUT_XOR (w) register accessor: GPIO output value XOR
  • INTERP0_ACCUM0 (rw) register accessor: Read/write access to accumulator 0
  • INTERP0_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0
    Reading yields lane 0’s raw shift and mask value (BASE0 not added).
  • INTERP0_ACCUM1 (rw) register accessor: Read/write access to accumulator 1
  • INTERP0_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1
    Reading yields lane 1’s raw shift and mask value (BASE1 not added).
  • INTERP0_BASE0 (rw) register accessor: Read/write access to BASE0 register.
  • INTERP0_BASE1 (rw) register accessor: Read/write access to BASE1 register.
  • INTERP0_BASE2 (rw) register accessor: Read/write access to BASE2 register.
  • INTERP0_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
    Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
  • INTERP0_CTRL_LANE0 (rw) register accessor: Control register for lane 0
  • INTERP0_CTRL_LANE1 (rw) register accessor: Control register for lane 1
  • INTERP0_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK).
  • INTERP0_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK).
  • INTERP0_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK).
  • INTERP0_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP).
  • INTERP0_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
  • INTERP0_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
  • INTERP1_ACCUM0 (rw) register accessor: Read/write access to accumulator 0
  • INTERP1_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0
    Reading yields lane 0’s raw shift and mask value (BASE0 not added).
  • INTERP1_ACCUM1 (rw) register accessor: Read/write access to accumulator 1
  • INTERP1_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1
    Reading yields lane 1’s raw shift and mask value (BASE1 not added).
  • INTERP1_BASE0 (rw) register accessor: Read/write access to BASE0 register.
  • INTERP1_BASE1 (rw) register accessor: Read/write access to BASE1 register.
  • INTERP1_BASE2 (rw) register accessor: Read/write access to BASE2 register.
  • INTERP1_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
    Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
  • INTERP1_CTRL_LANE0 (rw) register accessor: Control register for lane 0
  • INTERP1_CTRL_LANE1 (rw) register accessor: Control register for lane 1
  • INTERP1_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK).
  • INTERP1_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK).
  • INTERP1_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK).
  • INTERP1_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP).
  • INTERP1_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
  • INTERP1_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
  • SPINLOCK (rw) register accessor: Reading from a spinlock address will:
  • SPINLOCK_ST (r) register accessor: Spinlock state
    A bitmap containing the state of all 32 spinlocks (1=locked).
    Mainly intended for debugging.