Expand description
DW_apb_ssi has the following features:
- APB interface - Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.
- APB3 and APB4 protocol support.
- Scalable APB data bus width - Supports APB data bus widths of 8, 16, and 32 bits.
- Serial-master or serial-slave operation - Enables serial communication with serial-master or serial-slave peripheral devices.
- Programmable Dual/Quad/Octal SPI support in Master Mode.
- Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.
- Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.
- eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.
- DMA Controller Interface - Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.
- Independent masking of interrupts - Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.
- Multi-master contention detection - Informs the processor of multiple serial-master accesses on the serial bus.
- Bypass of meta-stability flip-flops for synchronous clocks - When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.
- Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.
- Programmable features:
- Serial interface operation - Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.
- Clock bit-rate - Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.
- Data Item size (4 to 32 bits) - Item size of each data transfer under the control of the programmer.
- Configured features:
- FIFO depth - 16 words deep. The FIFO width is fixed at 32 bits.
- 1 slave select output.
- Hardware slave-select - Dedicated hardware slave-select line.
- Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.
- Interrupt polarity - active high interrupt lines.
- Serial clock polarity - low serial-clock polarity directly after reset.
- Serial clock phase - capture on first edge of serial-clock directly after reset.
Modules§
- baudr
- Baud rate
- ctrlr0
- Control register 0
- ctrlr1
- Master Control register 1
- dmacr
- DMA control
- dmardlr
- DMA RX data level
- dmatdlr
- DMA TX data level
- dr0
- Data Register 0 (of 36)
- icr
- Interrupt clear
- idr
- Identification register
- imr
- Interrupt mask
- isr
- Interrupt status
- msticr
- Multi-master interrupt clear
- mwcr
- Microwire Control
- risr
- Raw interrupt status
- rx_
sample_ dly - RX sample delay
- rxflr
- RX FIFO level
- rxftlr
- RX FIFO threshold level
- rxoicr
- RX FIFO overflow interrupt clear
- rxuicr
- RX FIFO underflow interrupt clear
- ser
- Slave enable
- spi_
ctrlr0 - SPI control
- sr
- Status register
- ssi_
version_ id - Version ID
- ssienr
- SSI Enable
- txd_
drive_ edge - TX drive edge
- txflr
- TX FIFO level
- txftlr
- TX FIFO threshold level
- txoicr
- TX FIFO overflow interrupt clear
Structs§
- Register
Block - Register block
Type Aliases§
- BAUDR
- BAUDR (rw) register accessor: Baud rate
- CTRLR0
- CTRLR0 (rw) register accessor: Control register 0
- CTRLR1
- CTRLR1 (rw) register accessor: Master Control register 1
- DMACR
- DMACR (rw) register accessor: DMA control
- DMARDLR
- DMARDLR (rw) register accessor: DMA RX data level
- DMATDLR
- DMATDLR (rw) register accessor: DMA TX data level
- DR0
- DR0 (rw) register accessor: Data Register 0 (of 36)
- ICR
- ICR (r) register accessor: Interrupt clear
- IDR
- IDR (r) register accessor: Identification register
- IMR
- IMR (rw) register accessor: Interrupt mask
- ISR
- ISR (r) register accessor: Interrupt status
- MSTICR
- MSTICR (r) register accessor: Multi-master interrupt clear
- MWCR
- MWCR (rw) register accessor: Microwire Control
- RISR
- RISR (r) register accessor: Raw interrupt status
- RXFLR
- RXFLR (r) register accessor: RX FIFO level
- RXFTLR
- RXFTLR (rw) register accessor: RX FIFO threshold level
- RXOICR
- RXOICR (r) register accessor: RX FIFO overflow interrupt clear
- RXUICR
- RXUICR (r) register accessor: RX FIFO underflow interrupt clear
- RX_
SAMPLE_ DLY - RX_SAMPLE_DLY (rw) register accessor: RX sample delay
- SER
- SER (rw) register accessor: Slave enable
- SPI_
CTRL R0 - SPI_CTRLR0 (rw) register accessor: SPI control
- SR
- SR (r) register accessor: Status register
- SSIENR
- SSIENR (rw) register accessor: SSI Enable
- SSI_
VERSION_ ID - SSI_VERSION_ID (r) register accessor: Version ID
- TXD_
DRIVE_ EDGE - TXD_DRIVE_EDGE (rw) register accessor: TX drive edge
- TXFLR
- TXFLR (r) register accessor: TX FIFO level
- TXFTLR
- TXFTLR (rw) register accessor: TX FIFO threshold level
- TXOICR
- TXOICR (r) register accessor: TX FIFO overflow interrupt clear